Optimal wire-sizing formula under the Elmore delay model

Chen, Chung-Ping; Chen, Yao-Ping; Wong, D.F.

doi:10.1145/240518.240611

Cited by 69 publications

(47 citation statements)

References 8 publications

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“…For weighted sink delay objective, our algorithm MASM-BS can be applied to nets with tree topology by a similar technique as in [6]. That is we use an iterative algorithm to optimize the tree edges one at a time.…”

Section: Experimental Results and Concluding Remarksmentioning

confidence: 99%

“…For other objectives like minimizing maximum delay or minimizing area with delay bounds, the problems can be solved by the Lagrangian relaxation technique as in [6]. Basically, the Lagrangian relaxation technique reduces the problems into a sequence of problems of minimizing weighted sink delay, where the sink weights are just the Lagrange multipliers.…”

Section: Experimental Results and Concluding Remarksmentioning

confidence: 99%

“…For wire sizing alone, [3], [5], [16], and [17] considered a variant which does not divide a wire into segments. For the problem they considered, the set of choices of wire width is a continuous interval.…”

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confidence: 99%

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A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

Chu

Wong

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore some special properties of our problem and derive an optimal and very efficient algorithm modified active set method (MASM) to solve the resulting program. Given m buffers and a set of n discrete choices of wire width, the running time of our algorithm is O(mn 2 ) and is independent of the wire length in practice. For example, an instance of 100 buffers and 100 choices of wire width can be solved in 0.92 s. In addition, we extend MASM to consider simultaneous buffer insertion, buffer sizing, and wire sizing. The resulting algorithm MASM-BS is again optimal and very efficient. For example, with six choices of buffer size and 10 choices of wire width, the optimal solution for a 15 000 m long wire can be found in 0.05 s. Besides, our formulation is so versatile that it is easy to consider other objectives like wire area or power dissipation, or to add constraints to the solution. Also, wire capacitance lookup tables, or very general wire capacitance models which can capture area capacitance, fringing capacitance, coupling capacitance, etc. can be used.

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Section: Experimental Results and Concluding Remarksmentioning

confidence: 99%

Section: Experimental Results and Concluding Remarksmentioning

confidence: 99%

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A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

Chu

Wong

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…As VLSI technology continues to scale down, interconnect delay has become the dominant factor in deep submicron design [1]. With the continued scaling of process technology, the resistance per unit length of the interconnect continues to increase, the capacitance per unit length remains roughly constant and transistor or logic delay continues to decrease [2].…”

Section: Introductionmentioning

confidence: 99%

Buffer Insertion for Delay Minimization using An Improved PSO Algorithm

Karimi¹,

Ahmadi²

2014

Appl. Math. Inf. Sci.

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This paper considers the problem of interconnect wire delay in digital integrated circuits. The correct wire sizing and buffer insertion/sizing can reduce the interconnect delay. The interconnect wire is divided into segments and to optionally buffers are inserted between two adjacent segments. But it is important to select appropriate values for the size of buffers as well as the lengths and widths of segments to minimize the delay. Since the delay is a multi-dimensional function, its optimizing process is complex and time-consuming. In this paper we introduce an improved particle swarm optimization for delay minimization. The aim is to reduce the interconnect wire delay. This work is performed in 3 case studies. Sizing a chain of buffers without considering the wire delay is done in case study 1. Wire sizing alone and buffer insertion/sizing with wire sizing are dealt in case study 2 and case study 3 respectively. In these case studies, the our improved PSO results are matched with theoretical results while the proposed technique is very fast and more accurate than standard techniques.

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“…In fact, there have been a lot of works on it, e.g., the wire sizing and shaping without fringing capacitance [20,21], with fringing capacitance [22,23], under transmission line model [24], or with single-width sizing (1-WS) or two-width sizing (2-WS) [28]. Wire sizing for multi terminal nets have also been extensively studied [25][26][27].…”

Section: Introductionmentioning

confidence: 99%

Wire sizing with scattering effect for nanoscale interconnection

Shian

Jian

Asia and South Pacific Conference on Design Automation, 2006.

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Abstract-For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay significantly. Existing works on scattering effect are mostly performed using very complicated physics-based models, while the scattering impact on nanoscale VLSI interconnect and optimization have not been studied. In this paper, we first present a simple, closed-form scattering effect resistivity model based on extensive empirical studies on measurement data. Then we apply the proposed scattering model to revisit several classic wire sizing/shaping problems. Our experimental results show that if the scattering effect is ignored or characterized inaccurately beyond 65nm, the resulting interconnect optimization might be way off from the real optimal solution, e.g., up to 70% underestimation of the delay, or 20x oversizing. We also obtain the new closed-form wiresizing functions with consideration of scattering effects. I INTRODUCTIONS the feature size continues to shrink, the lateral dimension of conductors will be approaching the mesoscopic regime in which the diameter of the wire is in the range of or smaller than the mean free path of the electrons ( , about 40nm for copper at room temperature), and the electrical resistivity of metallic conductors is increased compared to the resistivity of bulky metal. The earliest work on this dates back to 1938, when an expression for the resistivity of metal thin films (1-dimensional) was derived by Fuchs [1]. Later on it was extended to 2-dimensional by the FS model [2] for thin/narrow wires. Basically, the FS model accounts for the surface scattering. Later on, the MS model [3] was developed to incorporate the grain boundary scattering, which also increases the wire resistivity. For both surface and grain boundary scattering effects, very complicated quantum mechanical effects can be applied to obtain the empirical parameters in FS or MS model [4,5].While MS and FS models have been tested with measurement data for polycrystalline nanowires [6][7][8], very few experimental results on copper (Cu) film or interconnect have been reported until recently, e.g., the size effect of copper thin film was studied in [9], and the resistivity of copper wires with widths under 50nm was reported in [10][11][12][13]. The key observation is that the resistivity of copper wires will increase significantly as the wires width decreases [9][10][11][12][13][14]. While exploratory structures such as carbon nanotubes are being studied as possible replacement of copper interconnect [15][16][17], at least by 22nm technology, it is not likely that copper will be replaced by carbon nanotube or other materials [15]. There are also efforts in manufacturing improvement to partially reduce the scattering effect of copper wires [18,19], but even so the scattering effect can no longer be ignored as the technology continues to scale down.A popular method to reduce the interconnection delay is wire sizing. In fact, there have be...

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Optimal wire-sizing formula under the Elmore delay model

Cited by 69 publications

References 8 publications

A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

Buffer Insertion for Delay Minimization using An Improved PSO Algorithm

Wire sizing with scattering effect for nanoscale interconnection

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