Optimal task placement to improve cache performance

Gebhard, Gernot; Altmeyer, Sebastian

doi:10.1145/1289927.1289968

Cited by 24 publications

(15 citation statements)

References 13 publications

(16 reference statements)

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“…Since the mapping of memory to cache is often statically prescribed by the hardware (Patterson and Hennessy 2014), a proper memory layout of the tasks is important even when the total number of occupied memory blocks fits into the cache. Gebhard and Altmeyer (2007) and Lunniss et al (2012) therefore tried to optimize the CRPDs by changing the layout of tasks in memory, subject to a static mapping of memory blocks to cache blocks. In our paper, we build upon the earlier work for FPPS by Lunniss et al (2012) and we generalize their approach to FPTS.…”

Section: Cache-related Pre-emption Delays (Crpds)mentioning

confidence: 99%

Fixed priority scheduling with pre-emption thresholds and cache-related pre-emption delays: integrated analysis and evaluation

et al. 2017

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Commercial off-the-shelf programmable platforms for real-time systems typically contain a cache to bridge the gap between the processor speed and main memory speed. Because cache-related pre-emption delays (CRPD) can have a significant influence on the computation times of tasks, CRPD have been integrated in the response time analysis for fixed-priority pre-emptive scheduling (FPPS). This paper presents CRPD aware response-time analysis of sporadic tasks with arbitrary deadlines for fixed-priority pre-emption threshold scheduling (FPTS), generalizing earlier work. The analysis is complemented by an optimal (pre-emption) threshold assignment algorithm, assuming the priorities of tasks are given. We further improve upon these results by presenting an algorithm that searches for a layout of tasks in memory that makes a task set schedulable. The paper includes an extensive comparative evaluation of the schedulability ratios of FPPS and FPTS, taking CRPD into account. The practical relevance of our work stems from FPTS support in AUTOSAR, a standardized development model for the automotive industry. Keywords Fixed-priority pre-emptive scheduling · Fixed-priority scheduling with pre-emption thresholds · Cache-related pre-emption delay · Response-time analysis B Reinder J. Bril

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Section: Cache-related Pre-emption Delays (Crpds)mentioning

confidence: 99%

Fixed priority scheduling with pre-emption thresholds and cache-related pre-emption delays: integrated analysis and evaluation

et al. 2017

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“…[22] exploits both cache partitioning and dynamic cache locking to to provide worst case performance estimates for multitasking systems. [6] stud ies the problem of placing multiple tasks in the cache to im prove cache performance. It proposes an ILP based approach to optimally placing multiple tasks in the cache.…”

Section: Related Workmentioning

confidence: 99%

Scratchpad Memory aware task scheduling with minimum number of preemptions on a single processor

Wan

Xue

2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-We propose a unified approach to the problem of scheduling a set of tasks with individual release times, deadlines and precedence constraints, and allocating the data of each task to the SPM (Scratchpad Memory) on a single processor system.Our approach consists of a task scheduling algorithm and an SPM allocation algorithm. The former constructs a feasible schedule incrementally, aiming to minimize the number of preemptions in the feasible schedule. The latter allocates a portion of the SPM to each task in an efficient way by employing a novel data structure, namely, the preemption graph. We have evaluated our approach and a previous approach by using six task sets. The results show that our approach achieves up to 20.31 % on WCRT (Worst-Case Response Time) reduction over the previous approach.

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“…In [10], a technique for rearranging the positions of tasks to improve the cache performance is presented. The interdependency relation of tasks is evaluated in order to determine a memory layout which maximizes the number of persistent cache sets for each task.…”

Section: Related Workmentioning

confidence: 99%

WCET-driven branch prediction aware code positioning

Plazar

Kleinsorge

Falk

et al. 2011

Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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In the past decades, embedded system designers moved from simple, predictable system designs towards complex systems equipped with caches, branch prediction units and speculative execution. This step was necessary in order to fulfill increasing requirements on computational power. Static analysis techniques considering such speculative units had to be developed to allow the estimation of an upper bound of the execution time of a program. This bound is called worst-case execution time (WCET). Its knowledge is crucial to verify whether hard real-time systems satisfy their timing constraints, and the WCET is a key parameter for the design of embedded systems.In this paper, we propose a WCET-driven branch prediction aware optimization which reorders basic blocks of a function in order to reduce the amount of jump instructions and mispredicted branches. We employed a genetic algorithm which rearranges basic blocks in order to decrease the WCET of a program. This enables a first estimation of the possible optimization potential at the cost of high optimization runtimes. To avoid time consuming repetitive WCET analyses, we developed a new algorithm employing integer-linear programming (ILP). The ILP models the worst-case execution path (WCEP) of a program and takes branch prediction effects into account. This algorithm enables short optimization runtimes at slightly decreased optimization results. In a case study, the genetic algorithm is able to reduce the benchmarks' WCET by up to 24.7% whereas our ILP-based approach is able to decrease the WCET by up to 20.0%.

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Optimal task placement to improve cache performance

Cited by 24 publications

References 13 publications

Fixed priority scheduling with pre-emption thresholds and cache-related pre-emption delays: integrated analysis and evaluation

Fixed priority scheduling with pre-emption thresholds and cache-related pre-emption delays: integrated analysis and evaluation

Scratchpad Memory aware task scheduling with minimum number of preemptions on a single processor

WCET-driven branch prediction aware code positioning

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