Optimal task assignment in multithreaded processors

Radojković, Petar; Cakarevic, Vladimir; Moretó, Miquel; Verdú, Javier; Pajuelo, Alex; Cazorla, Francisco J.; Nemirovsky, Mario; Valero, Mateo

doi:10.1145/2150976.2151002

Cited by 32 publications

(24 citation statements)

References 35 publications

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“…In this paper, we validate our methods with an industrial case study for a set of multithreaded network applications on an UltraSPARC T2 processor. This article is an extension of our previous work [44], which was published in …”

mentioning

confidence: 72%

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

Radojković

Carpenter

Moretó

et al. 2016

IEEE Trans. Comput.

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Abstract-The introduction of multicore/multithreaded processors, comprised of a large number of hardware contexts (virtual CPUs) that share resources at multiple levels, has made process scheduling, in particular assignment of running threads to available hardware contexts, an important aspect of system performance. Nevertheless, thread assignment of applications running on state-of-the art processors is an NP-complete problem. Over the years, numerous studies have proposed heuristic-based algorithms for thread assignment. Since the thread assignment problem is intractable, it is in general impossible to know the performance of the optimal assignment, so the room for improvement of a given algorithm is also unknown. It is therefore hard to decide whether to invest more effort and time to improve an algorithm that may already be close to optimal. In this paper, we present a statistical approach to the thread assignment problem. First, we present a method that predicts the performance of the optimal thread assignment, based on the observed performance of each thread assignment in a random sample. The method is based on Extreme Value Theory (EVT), a branch of statistics that analyses extreme deviations from the population mean. We also propose sample pruning, a method that significantly reduces the time required to apply the statistical method by reducing the number of candidate solutions that need to be measured. Finally, we show that, if no suitable heuristicbased algorithm is available, a sample of several thousand random thread assignments is enough to obtain, with high confidence, an assignment with performance close to optimal. The presented approach is architecture and application independent, and it can be used to address the thread assignment problem in various domains. It is especially well suited for systems in which the workload seldom changes. An example is network systems, which typically provide a constant set of services that are known in advance, with network applications performing a similar processing algorithm for each packet in the system. In this paper, we validate our methods with an industrial case study for a set of multithreaded network applications on an UltraSPARC T2 processor. This article is an extension of our previous work [44], which was published in

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confidence: 72%

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

Radojković

Carpenter

Moretó

et al. 2016

IEEE Trans. Comput.

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“…However, as the number of multi-threaded applications increases in a workload, the number of mapping configurations that must be evaluated to identify the application characteristics in the presence of co-runners and determine the optimal thread-mappings for performance and reliability improvement, can increase exponentially [21]. When the number of threads in a workload is very high, this exponential complexity makes the online resource usage detection and application thread-mappings very challenging and causes the characterization technique to have significant overhead.…”

Section: The Resense Frameworkmentioning

confidence: 99%

“…Mitigation involves mapping the applications in the thread-mapping configuration that ensures the lowest contention and performance degradation [33,20]. However, as the multi-threaded applications in a workload can create a varying number of threads, the number of thread-to-core-mapping configurations can increase exponentially [21]. As a result, determining the thread mapping that minimizes contention by online contention detection in all possible thread-mapping configurations has exponential complexity and makes mapping threads optimally to mitigate contention an NP-complete problem [59].…”

Section: Introductionmentioning

confidence: 99%

ReSense: A Unified Framework for Improving Performance and Reliability in Multicore Architectures

Dey

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Chip-multiprocessors (CMPs) have become ubiquitous in modern computing and the mainstream architecture for various platforms, including laptops, desktops, and large server machines. As technology scaling continues and more transistors are accommodated on the chip, the number of cores on CMPs is growing, and multi-core machines are scaling up to many-core machines. With this multi-core scaling, two major problems arise: shared-resource contention and soft errors or transient faults. Shared-resource contention can degrade an application's performance significantly, and soft errors increase the probability of incorrect application execution and the production of visible errors. To realize the full potential of multi-and many-core platforms, it is critical to ensure that applications in a workload not only execute e ciently and fast, but also correctly.In this dissertation, we develop a novel, general, and unified framework, ReSense, to address several challenges on multicore architectures including performance optimization, reliability improvement, power and thermal management. The framework includes five components: a general characterization methodology, a characterization metric, a sensitivity score, a thread mapping algorithm, and a run-time system. An instance of the framework is applied in two phases: characterization and mapping. The characterization phase utilizes the general characterization methodology and characterization metric to identify application characteristics without considering any co-runner(s). It generates a resource-sensitivity score for each application in a workload. In the mapping phase, the run-time system uses a thread-mapping algorithm and the sensitivity scores of the applications in a workload to c Abstract d determine the thread-mappings that optimize the objective function of the targeted problem.To demonstrate the utility and e ectiveness of ReSense, we use it to address the problems of shared-resource contention and soft errors for multi-threaded applications. For the resource contention problem, the characterization methodology determines how a multi-threaded application's performance is a ected as it shares a resource in the memory hierarchy. A sensitivity score based on resource contention is produced for each application in a workload.The run-time system uses the resource-contention sensitivity scores and a thread-mapping algorithm to allocate threads from a workload to core to mitigate shared-resource contention, thus improving response time and throughput.For the soft error problem, the characterization methodology determines how a multithreaded application's vulnerability to soft errors in shared caches is a ected by its resource occupancy duration. A sensitivity score based on cache occupancy is produced for each application in a workload. The run-time system uses the cache-occupancy sensitivity scores and a thread-mapping algorithm to allocate workload threads to cores to reduce the occupancy in the shared caches, thus reducing cache vulnerability.Both minimizing...

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“…More system throughput was generated by the proposed scheduling policy, but it did not conduct real-time migration, so the policy was a static dispatching policy with a priori knowledge. Radojkovic et al executed a large quantity of task assignments among all possible combinations, such that the best observed one was statistically within the top performance group [48]. Their design spent 2 hours on executing every 5000 assignments, and every new set of threads needed such a process.…”

Section: Homogeneous Microprocessorsmentioning

confidence: 99%

“…Time complexity in searching for the optimal scheduling will increase exponentially if we want to evaluate all the threads across all cores, irrelevant to the kind of metric we employ. Ultimately, it merges to an NP-hard problem [48], and the time complexity is O(n u ), where n is the total number of tasks and u is the number that an MMMP supports simultaneously [109,110].…”

Section: Increasing Capacitymentioning

confidence: 99%

A Hardware and Software Integrated Approach for Adaptive Thread Management in Multicore Multithreaded Microprocessors

Weng¹

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The Multicore Multithreaded Microprocessor maximizes parallelism on a chip for the optimal system performance, such that its popularity is growing rapidly in high-performance computing. It increases the complexity in resource distribution on a chip by leading it to two directions: isolation and unification. On one hand, multiple cores are implemented to deliver the computation and memory accessing resources to more than one thread at the same time. Nevertheless, it limits the threads' access to resources in different cores, even if extensively demanded. On the other hand, simultaneous multithreaded architectures unify the domestic execution resources together for concurrently running threads. In such an environment, threads are greatly affected by the inter-thread interference. Moreover, the impacts of the complicated distribution are enlarged by variation in workload behaviors. As a result, the microprocessor requires an adaptive management scheme to schedule threads throughout different cores and coordinate them within cores.In this study, an adaptive thread management scheme was proposed, integrating both hardware and software approaches. The instruction fetch policy at the hardware level took the responsibility by prioritizing domestic threads, while the Operating System scheduler at the software level was used to pair threads dynamivi cally to multiple cores. The tie between them was the proposed online linear model, which was dynamically constructed for every thread based on data misses by the regression algorithm. Consequently, the hardware part of the proposed scheme proactively granted higher priority to the threads with less predicted long-latency loads, expecting they would better utilize the shared execution resources. Meanwhile, the software part was invoked by such a model upon significant changes in the execution phases and paired threads with different demands to the same core to minimize competition on the chip. The proposed scheme was compared to its peer designs and overall 43% speedup was achieved by the integrated approach over the combination of two baseline policies in hardware and software, respectively. The overhead was examined carefully regarding power, area, storage and latency, as well as the relationship between the overhead and the performance.

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Optimal task assignment in multithreaded processors

Cited by 32 publications

References 35 publications

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

ReSense: A Unified Framework for Improving Performance and Reliability in Multicore Architectures

A Hardware and Software Integrated Approach for Adaptive Thread Management in Multicore Multithreaded Microprocessors

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