Optimal system-on-chip test scheduling

2007

IEEE Trans. VLSI Syst.

Abstract-Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method.

Section: A Test-length Selection Problemsupporting

confidence: 52%

Section: A Test-length Selection Problemmentioning

confidence: 99%

Wafer-Level Modular Testing of Core-Based SoCs

2007

IEEE Trans. VLSI Syst.

“…In our work, without loss of generality, we use the normalized function fc i (p * i ) = (log 10 (p * i + 1)/ log 10 p i ) to represent this relationship. A similar relationship was used in [30]. We have verified that this empirical relationship matches the "fault coverage curve" for the ISCAS benchmark circuits.…”

Section: B Test-length and Tam Optimization Problem: P Tltwsmentioning

confidence: 67%

“…Otherwise, we model the relationship between fault coverage and the number of patterns with an exponential function. It is well known in the testing literature that the fault coverage for stuck-at faults increases rapidly initially as the pattern count increases, but it flattens out when more patterns are applied to the circuit under test [29], [30]. In our work, without loss of generality, we use the normalized function fc i (p * i ) = (log 10 (p * i + 1)/ log 10 p i ) to represent this relationship.…”

Section: B Test-length and Tam Optimization Problem: P Tltwsmentioning

confidence: 99%

Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

2009

Abstract-Wafer-level testing (wafer sort) is used in the semiconductor industry to reduce packaging and test cost. However, a large number of wafer-probe contacts lead to higher yield loss. Therefore, it is desirable that the number of chip pins contacted by tester channels during wafer sort be kept small to reduce the yield loss resulting from improper contacts. Since test time and the number of contacted chip pins are major practical constraints for wafer sort, not all scan-based digital tests can be applied to the die under test. We propose an optimization framework based on mathematical programming (integer linear programming, nonlinear programming, and geometric programming) and fast heuristic methods. This framework addresses test-access mechanism (TAM) optimization and test-length selection for wafer-level testing of core-based digital system-on-chips (SoCs). The objective here is to design a TAM architecture and determine test lengths for the embedded cores such that the overall SoC defect-screening probability at wafer sort is maximized. Defect probabilities for the embedded cores, obtained using statistical yield modeling, are incorporated in the optimization framework. Simulation results are presented for five of the ITC'02 SoC Test benchmarks.

“…Otherwise, we model the relationship between fault coverage and the number of patterns with an exponential function. It is well known in the testing literature that the fault coverage for stuck-at faults increases rapidly initially as the pattern count increases, but it flattens out when more patterns are applied to the circuit under test [24], [25]. In our work, without loss of generality, we use the normalized function f ci(p * i ) = log 10 (p * i +1) log 10 p i to represent this relationship.…”

Section: B Test-length and Tam Optimization Problem: Pt Lt W Smentioning

confidence: 99%

Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs

20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07)

2007

Abstract-Wafer-level testing (wafer sort) is used in the semiconductor industry to reduce packaging and test cost. However, a large number of wafer probe contacts leads to higher yield loss. Therefore, it is desirable that the number of chip pins contacted by tester channels during wafer sort be kept small to reduce the yield loss resulting from improper contacts. Since test time and the number of contacted chip pins are major practical constraints for wafer sort, not all scan-based digital tests can be applied to the die-under-test. We propose an optimization framework that addresses test access mechanism (TAM) optimization and test-length selection for wafer-level testing of core-based digital SoCs. The objective here is to design a TAM architecture and determine test-lengths for the embedded cores such that the overall SoC defect screening probability at wafer sort is maximized. Defect probabilities for the embedded cores, obtained using statistical yield modeling, are incorporated in the optimization framework. Simulation results are presented for five of the ITC'02 SoC Test benchmarks.