Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs)

Pull Down Network Minimization, Based on Equivalent Functions Concept, in DCVS Circuit Design

“…It does have a well defined algorithm and produces an appropriate implementation of a DCVS pull-down network [4]. A Binary Decision Diagram (BDD) is a rooted acyclic directed graph which can model Boolean functions [5].…”

“…With this method the implementation stage of the pulldown trees doesn't have a well defined algorithm and is rather heuristic. It is also proved in [4] that this method is not able to produce the best optimized pull-down network.…”

“…The BDD implementation of a Boolean function can be simplified with Sub-graph Elimination rule and Node Elimination rule and some of the nodes can be dropped out [4]. Applying the above rules on a complete OBDD will produce a Reduced Ordered Binary Decision Diagram (ROBDD) on which none of these rules can be applied anymore.…”

A system for calculating the Greatest Common Denominator implemented using Asynchrobatic Logic

“…PFAL was chosen, as it is one of the simplest adiabatic logic families and in appropriate applications, it has the potential to operate in a fully reversible fashion [6]. The link with DCVSL is very useful, as there are efficient design methodologies for DCVSL circuits [7] [8], that can be used to design PFAL gates. III.…”

Using Positive Feedback Adiabatic Logic to implement Reversible Toffoli Gates

“…The design of logic functions for all dual-rail adiabatic logic families can be achieved by using the same procedures that may be used for DCVSL. These methods are either a Quine-McClusky style [17] or one based upon Ordered Binary Decision Diagrams (OBDD) [18] [19], or extensions thereto. A reversible buffer implemented using PFAL is shown in Fig.…”