Optimal robust compression of test responses

Karpovsky, Mark G.; Nagvajara, P.

doi:10.1109/12.46290

Cited by 48 publications

(8 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, neither HSC nor DSC does provide an adequate measure of fault coverage because they both rely on estimates of error detection probabilities. Quadratic functions compaction (QFC) uses quadratic functions to construct the space compaction circuits, and has been shown to reduce aliasing errors [40]. In QFC, the observed output responses of the CUT are processed and compressed in a serial fashion based on a function of the type , where and are blocks of length , for .…”

Section: Brief Overview Of Test Compaction Techniquesmentioning

confidence: 99%

Fault Simulation and Response Compaction in Full Scan Circuits Using HOPE

Das

Ramamoorthy

Assaf

et al. 2005

IEEE Trans. Instrum. Meas.

View full text Add to dashboard Cite

This paper presents results on fault simulation and response compaction on ISCAS 89 full scan sequential benchmark circuits using HOPE-a fault simulator developed for synchronous sequential circuits that employs parallel fault simulation with heuristics to reduce simulation time in the context of designing space-efficient support hardware for built-in self-testing of very large-scale integrated circuits. The techniques realized in this paper take advantage of the basic ideas of sequence characterization previously developed and utilized by the authors for response data compaction in the case of ISCAS 85 combinational benchmark circuits, using simulation programs ATALANTA, FSIM, and COMPACTEST, under conditions of both stochastic independence and dependence of single and double line errors in the selection of specific gates for merger of a pair of output bit streams from a circuit under test (CUT). These concepts are then applied to designing efficient space compression networks in the case of full scan sequential benchmark circuits using the fault simulator HOPE.

show abstract

Section: Brief Overview Of Test Compaction Techniquesmentioning

confidence: 99%

Fault Simulation and Response Compaction in Full Scan Circuits Using HOPE

Das

Ramamoorthy

Assaf

et al. 2005

IEEE Trans. Instrum. Meas.

View full text Add to dashboard Cite

show abstract

“…Quadratic functions compaction (QFC) [22] uses quadratic functions to construct the space compaction circuits, and has been shown to reduce aliasing. In QFC, the observed output responses of the CUT are processed and compressed in a serial fashion based on a function of the type , where and are blocks of length , for .…”

Section: Overview Of Test Compaction Techniquesmentioning

confidence: 99%

“…The principal idea in space compaction is to compress functional test outputs of the CUT possibly into one single test output line to derive the CUT signature without sacrificing too much information in the process. Generally, space compression has been accomplished using gates in cascade or in a tree structure [18], [21], [22], [28]. We will adopt a combination of both cascade and tree structures (cascade-tree) for our framework with , , and operators.…”

Section: Designing Compaction Tree Based On Sequence Characterizmentioning

confidence: 99%

Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering

Das

Liang

Petriu

et al. 2002

IEEE Trans. Instrum. Meas.

View full text Add to dashboard Cite

The synthesis of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the design and manufacture of today's sophisticated VLSI circuits, and a number of efficient algorithms have been proposed in the literature for this purpose. The subject paper reports new techniques that facilitate designing such space-efficient BIST support circuits using knowledge of compact test sets, with the target objective of minimizing the storage requirements for the circuit under test (CUT), while retaining the fault coverage information as best as possible. The suggested techniques take advantage of some well-known concepts of conventional switching theory, particularly those of cover table and frequency ordering, as commonly utilized in the minimization of switching functions, in conjunction with a new measure of failure probability in case of stochastic dependence of line errors, besides knowledge of Hamming distance, sequence weights, and derived sequences as previously used by the authors in sequence characterization, in the selection of specific logic gates for merger of an arbitrary number of output bit streams from the CUT. The outputs coming out of the space compactor may eventually be fed into a time compactor to derive the CUT signatures. The developed techniques guarantee good design with high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. Design algorithms are provided in the paper, and the simplicity and ease of their implementations are demonstrated with various examples. In particular, the paper gives results on extensive simulation runs on the ISCAS 85 combinational benchmark circuits with ATALANTA, FSIM, and COMPACTEST programs which confirm the merit of the approaches under conditions of both stochastic independence and dependence of multiple line output errors. A performance comparison of the designed space compactors with conventional linear parity tree space compactors as benchmark is also provided, which demonstrates the enhanced tradeoff for the new circuits in terms of fault coverage and the CUT resources consumed in comparison with the existing design methodologies.

show abstract

“…Thii techsique is often used for test vector compression in testing VLSI chips and image data compression [49,50,51,52]. As far as we know, little work hm been done in using information theory to compress instructions and to reduce instruction memory usage, nor has the information content of addressing information in instruction memory been adequately defiied.…”

Section: Programming Modelmentioning

confidence: 99%

Gt-Ep

Tan

Russ

Alford

1991

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

This paper presents the design and development of a novel processor architecture targeted for high performance real-time applications. The processor consists of four primary components: input devices, output devices, a dataflow processing unit (DPU), and a data.flow control unit (DCU). The central element of the processor is the DPU which consumes data from input devices and produces data to output deviees. The flow of data for the DPU is orchestrated by the DCU. Implemented in three silicon-compiled VLSI chips (one for the DPU and two for the DCU), the design utilizes modem, advanced computer design concepts and principles to formulate a novel architecture errsfted for the target applications. This processor is designated as the "Executive Processor" or GT-EP. 1

show abstract

Optimal robust compression of test responses

Cited by 48 publications

References 7 publications

Fault Simulation and Response Compaction in Full Scan Circuits Using HOPE

Fault Simulation and Response Compaction in Full Scan Circuits Using HOPE

Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering

Gt-Ep

Contact Info

Product

Resources

About