Proceedings of the Design Automation &Amp; Test in Europe Conference 2006
DOI: 10.1109/date.2006.243983
|View full text |Cite
|
Sign up to set email alerts
|

Optimal Periodic Testing of Intermittent Faults In Embedded Pipelined Processor Applications

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
20
0
6

Year Published

2008
2008
2021
2021

Publication Types

Select...
4
3

Relationship

0
7

Authors

Journals

citations
Cited by 27 publications
(31 citation statements)
references
References 9 publications
0
20
0
6
Order By: Relevance
“…Unlike most published studies, such as [20][21][22][23][24][25], the developed mathematical model considers the specifics of the architecture and application of modern avionics systems and can be used for any law of distribution of the operating time to permanent failure and intermittent fault. The described model might be further developed in order to divide the NFF events to intermittent faults and false alarms of the BITE.…”
Section: Discussionmentioning
confidence: 99%
See 2 more Smart Citations
“…Unlike most published studies, such as [20][21][22][23][24][25], the developed mathematical model considers the specifics of the architecture and application of modern avionics systems and can be used for any law of distribution of the operating time to permanent failure and intermittent fault. The described model might be further developed in order to divide the NFF events to intermittent faults and false alarms of the BITE.…”
Section: Discussionmentioning
confidence: 99%
“…The ADCN communications network comprises 16 AFDX switches and corresponding cables. The switches perform connection of 8 IOMs, 22 CPIOMs, and 50 LRUs with AFDX interface [4,5]. To reduce the number of connections from the cockpit control panel to avionics cabin computers, the controller area network (CAN) bus is used for the A380 avionics [6].…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…The production cost per sold chip 3 can be calculated by the following equation to evaluate different redundancy configurations (12) where, C core manu , C core AT E , and C core burn−in indicate the manufacturing cost, ATE cost for applying test patterns, and burn-in cost per fabricated core, respectively. Note that, test cost includes both ATE cost C core AT E and burn-in cost C core burn−in .…”
Section: Proposed Cost Modelmentioning
confidence: 99%
“…It is important to note, effective online testing techniques (e.g., [2,12,21]) are essential to identify functioning cores in manycore systems for the success of the above test cost reduction methodology. With increasingly adverse reliability threats for nanometer-scale VLSI circuits, we believe such techniques are available in future large-scale manycore systems.…”
Section: Introductionmentioning
confidence: 99%