Optimal circuits for parallel multipliers

Abstract

We present new design and analysis techniques for the synthesis of parallel multiplier circuits that have smaller predicted delay than the best current multipliers. In [4], Oklobdzija et al. suggested a new approach, the Three-Dimensional Method (TDM), for Partial Product Reduction Tree (PPRT) design that produces multipliers that outperform the current best designs. The goal of TDM is to produce a minimum delay PPRT using full adders. This is done by carefully modeling the relationship of the output delays to the input delays in an adder and, then, interconnecting the adders in a globally optimal way. Oklobdzija et al. suggested a good heuristic for finding the optimal PPRT, but no proofs about the performance of this heuristic were given. We provide a formal characterization of optimal PPRT circuits and prove a number of properties about them. For the problem of summing a set of input bits within the minimum delay, we present an algorithm that produces a minimum delay circuit in time linear in the size of the inputs. Our techniques allow us to prove tight lower bounds on multiplier circuit delays. These results are combined to create a program that finds optimal TDM multiplier designs. Using this program, we can show that, while the heuristic used in [4] does not always find the optimal TDM circuit, it performs very well in terms of overall PPRT circuit delay. However, our search algorithms find better PPRT circuits for reducing the delay of the entire multiplier.

Arithmetic optimization for custom instruction set synthesis

“…An appropriate final adder [5] computes the sum S + C. Compressor trees were further optimized for delay by Oklobdzija et al [1], [2]. They introduced the Three Greedy Approach (TGA), which algorithmically constructs delay-optimal compressor trees and can account for input bits with non-uniform arrival times.…”

Adding limited reconfigurability to superscalar processors

“…To validate this result, the VHDL code for both the balanced and unbalanced trees was written and synthetized in UMC 0.18µm technology. Both trees have been obtained with an algorithm similar to the Three-Greedy Approach [84]. The experimental value for the ratio Delay CP A /Delay CSA is 5.4, quite close to the theoretical value of 5.…”

“…High-radix approaches and Booth recoding [96] combine several bits or use redundant coding to process more than one bit in a single iteration, and can use a small tree of CSAs to form the partial products. They may increase the speed of the multiplier in some cases, but not all [84]. However, redundant coding implies the use of signed numbers, thus adding sign-extension hardware to the partial products generation.…”

“…However, this would slightly increase the number of levels in the tree, although the speed of these compressors can be optimized [62]. Higher order compressors may be built [66], such as a 9-to-2 compressor described in [81]; the best solution to reduce the partial products is to optimize the entire compressor tree [67,84]. The final adder can be any fast adder for the target technology.…”

“…The corresponding timing, area and power reports are also presented. All designs were written in VHDL, with the CSA compressor tree generated in Verilog by an approach similar to the Three-Greedy approach described in [84]. They were then synthesized on Unified Microelectronics Corporation's [153] 0.18µm technology using Synopsys' [151] Design Compiler and the Artisan libraries.…”