Optimal choice for phase margin on mm-Wave PLL frequency synthesizer for 5G wireless communications systems

Berber, Zakia; Kameche, Samir

doi:10.1109/sds.2018.8370447

Cited by 2 publications

(5 citation statements)

References 8 publications

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“…Outside the loop bandwidth, the PN is multiplied by the closed-loop transfer function [16]. So, the total output PN reported in [23] can be expressed by the general equation 4, while the transfer function of the closed-loop reported by [24] may be described by (5).…”

Section: Phase Noisementioning

confidence: 99%

“…Outside the loop bandwidth, the PN is multiplied by the closed‐loop transfer function [16]. So, the total output PN reported in [23] can be expressed by the general equation (4), while the transfer function of the closed‐loop reported by [24] may be described by (5).

P {normalN}_{Tot}^{2} = X^{2} + Y^{2} + Z^{2}

where PN Tot 2 is the total PN power at the output, X 2 is the noise power at the output due to PN N and PN Ref , Y 2 is the noise power at the output due to PN CP and Z 2 is the noise power at the output due to PN VCO

K ()(, s) = \frac{G ()(, s)}{(][, 1 + H ()(, s) \cdot G ()(, s))}

where G ( s ) is the forward loop gain and it is given by

G ()(, s) = \frac{K_{φ} \cdot Z ()(, s) \cdot K_{vco}}{s}

K φ and K VCO are the transfer function of the CP and VCO, respectively.…”

Section: Background and Motivationmentioning

confidence: 99%

“…According to (1), N = (1620–1720). The third‐order passive loop filter is designed with 45° phase margin and 1 MHz loop bandwidth. According to [24, 26], these parameter values are considered as optimal to design PLL synthesiser for E‐band frequency. The PN oscillators using the broadband floor and corner frequency is specified in both of the TCXO and VCO. o For the reference PN : it is specified with −170 dBc/Hz PN Floor (PN Floor ), 10 kHz corner frequency and 10 Hz flicker corner. o For the VCO PN : it is specified with −160 dBc/Hz floor, 100 kHz corner frequency and 10 Hz flicker corner. The prescaler PN is specified with two corner PN methods.…”

Section: Design and Simulationmentioning

confidence: 99%

See 2 more Smart Citations

Design of integer‐ N PLL frequency synthesiser for E‐band frequency for high phase noise performance in 5G communication systems

Berber¹,

Kameche²,

Benkhelifa

2020

IET Networks

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A phase-locked loop (PLL) frequency synthesiser is designed for 5G E-band frequency. ADF4155-PLL chip with an external (loop filter, prescaler, VCO and an external reference oscillator) is simulated using the ADIsimPLL tool. With a thirdorder passive filter having 1 MHz loop bandwidth and 45° phase margin, simulation results show that the proposed synthesiser achieves a total phase noise (PN) of −81.50 and −115.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for (71-76 GHz) and −80.39 and −114.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for the highest (81-86 GHz) 5G frequency range even if −160 dBc/Hz VCO noise floor and −170dBc/Hz reference PN floor are integrated in the design. Also, the performance of the system in terms of RMS jitter and reference spurs are verified. The proposed synthesiser for 5G application presents very low reference spurs (−113, −112 dBc) at 50 MHz offset frequency and low RMS jitter (0.39, 0.40 ps) for 70 and 80 GHz frequency band, respectively.

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Section: Phase Noisementioning

confidence: 99%

P {normalN}_{Tot}^{2} = X^{2} + Y^{2} + Z^{2}

K ()(, s) = \frac{G ()(, s)}{(][, 1 + H ()(, s) \cdot G ()(, s))}

where G ( s ) is the forward loop gain and it is given by

G ()(, s) = \frac{K_{φ} \cdot Z ()(, s) \cdot K_{vco}}{s}

K φ and K VCO are the transfer function of the CP and VCO, respectively.…”

Section: Background and Motivationmentioning

confidence: 99%

Section: Design and Simulationmentioning

confidence: 99%

See 1 more Smart Citation

Design of integer‐ N PLL frequency synthesiser for E‐band frequency for high phase noise performance in 5G communication systems

Berber¹,

Kameche²,

Benkhelifa

2020

IET Networks

View full text Add to dashboard Cite

show abstract

“…Higher phase margins can be decreasing and flatting the peaking around the loop bandwidth but can sacrifice switching speed of the PLL on the other hand. Conversely, if the phase margin is low, this tends to be peaking in the closed loop response and ringing in the PLL transient response (Zakia and Samir, 2018). So, for the loop stability, it would be better to design the synthesizer with a phase margin greater than 0 degree and less than 90 degrees as described in (Zakia and Samir, 2018) and expressed in (13).…”

Section: Loop Filter Designmentioning

confidence: 99%

“…Also, the loop filter component is used to achieve a desired PLL transfer function and to implement desired poles and zeros for realizing a given open loop transfer function. Furthermore, in combination with the charge pump, it sets the overall open loop gain of the system (Zakia and Samir, 2018). Considering this association, the leakage current produced by the Charge Pump transistors can have a great influence on the performance of the system.…”

Section: Introductionmentioning

confidence: 99%

High tolerance of charge pump leakage current in Integer-N PLL frequency synthesizer for 5G networks

Berber

Kameche

Benkhelifa

2019

Simulation Modelling Practice and Theory

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One of the most promising solutions for the future fifth generation communication systems is to utilize millimeter wave (mm-W) radio frequencies. There is, however, little works about Phase Locked Loop (PLL) frequency synthesizer designed for mm-W band frequency for 5G applications. This article discusses integer PLL architecture for frequency synthesis; it targets the highest range of 5G mmW [81-86] GHz using ultra-wide channel spacing of 1GHz. This work investigates the design of a third passive loop filter for frequency synthesizer using a Phase Frequency Detector and a current switch Charge Pump such as analog devices ADF4155. The critical performance for the Charge Pump depends on the leakage current produced by the technology of its transistors. This undesirable current can have a high impact on the loop stability. However, by optimizing PLL filter parameters, the synthesizer was able to tolerate up to 117 nA. With such a high leakage current, a high performance of the system was achieved. As a result, less than −71 dBc reference spur level at 50 MHz offset frequency was ensured and 3.23 µs settling time for a hopping frequency of 5 GHz was achieved.

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Optimal choice for phase margin on mm-Wave PLL frequency synthesizer for 5G wireless communications systems

Cited by 2 publications

References 8 publications

Design of integer‐ N PLL frequency synthesiser for E‐band frequency for high phase noise performance in 5G communication systems

Design of integer‐ N PLL frequency synthesiser for E‐band frequency for high phase noise performance in 5G communication systems

High tolerance of charge pump leakage current in Integer-N PLL frequency synthesizer for 5G networks

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