Optimal allocation and binding in high-level synthesis

Rim, M.; Jain, Rajiv; Leone, Renato De

doi:10.1109/dac.1992.227850

Cited by 32 publications

(19 citation statements)

References 11 publications

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“…The second group tries to address the global optimality and performs simultaneous functional unit and register binding. Representative algorithms include simulated annealing [7][8] [18], simulated evolution [21], and ILP (integer linear programming) [13] [26]. Since the subtasks of high-level synthesis are highly interrelated, simultaneous optimization approaches try to consider all the involved optimization parameters together and explore the combined solution space for overall better results.…”

Section: Related Workmentioning

confidence: 99%

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Chen

Cong

Fan

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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Section: Related Workmentioning

confidence: 99%

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Chen

Cong

Fan

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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“…The first group performs simultaneous functional unit and register binding. Representative algorithms include simulated annealing [5,9,24], simulated evolution [29], and integer linear programming (ILP) [13,35]. Since the subtasks of behavioral synthesis are highly interrelated, simultaneous optimization approaches try to consider all the involved optimization parameters together for globally better results.…”

Section: Related Workmentioning

confidence: 99%

Platform-based resource binding using a distributed register-file microarchitecture

Cong¹,

Fan²

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing interisland connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA platform, our experimental results show a 2X logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach.

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“…The researches in system level co-synthesis address on two main issues. The first issue is to optimize the selection and mapping of the system's functional blocks onto a set of processing elements (PE), like CPUs, digital signal processors (DSPs) and application-specific cores, etc [6,7]. The second issue is to optimize the communication architecture between the processing elements [8,9,10,11].…”

Section: Introductionmentioning

confidence: 99%

On-Chip Bus Architecture Optimization for Multi-core SoC Systems

Lien

Chen

Shih

2007

Software Technologies for Embedded and Ubiquitous Systems

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Abstract. With the significant driving force from the application domains, modern embedded systems are designed over heterogeneous multicore SoC platforms. When more and more functions are integrated into one system, the designs of embedded systems have become more and more complicated. In particular, most of embedded multimedia applications are data intensive. Performance bottleneck are often caused by inappropriate bus architecture design within the system. In this paper, we present the algorithms for bus architecture optimization in MFASE. The algorithm takes the workloads in the system and their timing behavior requirements into account. The goal is to minimize the number of buses in the system without violating timing requirements. We prove that the minimzation problem is NP-hard and develop a heuristic algorithm. We evaluate the algorithm with extensive simulations. The performance results show that the algorithm reduce up to 80% of the bus cost and performs as well as optimal exponential algorithm does.

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Optimal allocation and binding in high-level synthesis

Cited by 32 publications

References 11 publications

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Platform-based resource binding using a distributed register-file microarchitecture

On-Chip Bus Architecture Optimization for Multi-core SoC Systems

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