Optical Routing for 3D System-On-Package

Minz, J.R.; Thyagaraja, S.; Lim, Sung Kyu

doi:10.1109/date.2006.244180

Cited by 7 publications

(5 citation statements)

References 13 publications

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“…The many recent advances in nanophotonics devices have demonstrated great on-chip integration potential in nanoscale optical modulators, photo-detectors, couplers, switches, waveguides and WDM (Wavelength Division Multiplexing) devices. Meanwhile researches on photonics device modeling (e.g., [7]) and on-chip integration (e.g., [9][10][11][12][13][14]) have also introduced new opportunities and challenges to the traditional architectural and physical design methodologies. Specifically, on-chip networks and special architecture designs have been proposed (e.g., [10,13,15]) to enable high throughput network communication with on-chip nanophotonic WDM links.…”

Section: Introductionmentioning

confidence: 99%

“…At physical design level, however, studies for efficient onchip photonics interconnect synthesis have been limited. An early work by [9] employed straight line single channel optical waveguides to perform system-on-package optical routing under some timing consideration. However, physical characteristics were not considered for photonic devices.…”

Section: Introductionmentioning

confidence: 99%

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GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing

Ding,

Yu,

Pan

2014

Preprint

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In this paper, we examine the integration potential and explore the design space of low power thermal reliable on-chip interconnect synthesis featuring nanophotonics Wavelength Division Multiplexing (WDM). With the recent advancements, it is foreseen that nanophotonics holds the promise to be employed for future on-chip data signalling due to its unique power efficiency, signal delay and huge multiplexing potential. However, there are major challenges to address before feasible on-chip integration could be reached. In this paper, we present GLOW, a hybrid global router to provide low power opto-electronic interconnect synthesis under the considerations of thermal reliability and various physical design constraints such as optical power, delay and signal quality. GLOW is evaluated with testing cases derived from ISPD07-08 global routing benchmarks. Compared with a greedy approach, GLOW demonstrates around 23%-50% of total optical power reduction, revealing great potential of on-chip WDM interconnect synthesis.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing

Ding,

Yu,

Pan

2014

Preprint

View full text Add to dashboard Cite

show abstract

“…WDM allows for multiple signals to be transmitted simultaneously, facilitating higher throughput. The current technology is mature enough to allow this integration, thanks to CMOScompatible optical components, such as light sources [10], waveguides [11], modulators [16], [17], and detectors [18], [21].…”

Section: Introductionmentioning

confidence: 99%

Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC)

Beux

Trajković

O’Connor

et al. 2011

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip

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Trends in design of the next generation of Multi-Processors System on Chip (MPSoC) point to 3D integration of thousand of processing elements, requiring high performance interconnect for high throughput and low latency communications. Optical on-chip interconnects enable significantly increased bandwidth and decreased latency. They are thus considered as one of the most promising paradigms for the design of such system. However, existence of interfaces between electronic and photonic signals implies strong constraints on the layout of the 3D architecture and may impact the architecture scalability. In this paper, we propose and evaluate a possible layout for an optical Network-on-Chip used to interconnect processing elements located on different electrical layers.

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“…The methodology allows for constraint based optimization in terms of latency and insertion loss. Similarly, Minz et al have devised a synthesis tool for timing-driven optimization of optical waveguide placement in an on-chip network [18]. VANDAL is a place-and-route tool for on-chip photonic architectures which uses a library of modeled and characterized components, and includes automation tools for rapid design and synthesis [19].…”

Section: B Cad Toolsmentioning

confidence: 99%

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

Chan

Hendry

Bergman

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

107

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Abstract-Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely highbandwidth density and energy-efficient links for on-chip and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this paper, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment. We present a case study of two different photonic networks-on-chip to demonstrate how our improved understanding and modeling of the physical-layer details of photonic communications can be used to better understand the system-level performance impact.Index Terms-Optical communications, optical crosstalk, optical losses, photonic interconnection networks, simulation software, system analysis and design.

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Optical Routing for 3D System-On-Package

Cited by 7 publications

References 13 publications

GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing

GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing

Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC)

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

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