Opportunities of using artificial intelligence in hardware verification

Dinu, Anca; Ogrutan, Petre

doi:10.1109/siitme47687.2019.8990751

Cited by 9 publications

(4 citation statements)

References 2 publications

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“…Functional verification, the application of which is automated in the present work, is one of the most time consuming steps in the manufacturing process of integrated circuits [4]. This process consists in checking the design functionality (which is implemented through a Hardware Description Language, or HDL) against the specification of the system.…”

Section: Functional Verification: Implementation and Challengesmentioning

confidence: 99%

Coverage Fulfillment Automation in Hardware Functional Verification Using Genetic Algorithms

Danciu

Dinu

2022

Applied Sciences

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The functional verification process is one of the most expensive steps in integrated circuit manufacturing. Functional coverage is the most important metric in the entire verification process. By running multiple simulations, different situations of DUT functionality can be encountered, and in this way, functional coverage fulfillment can be improved. However, in many cases it is difficult to reach specific functional situations because it is not easy to correlate the required input stimuli with the expected behavior of the digital design. Therefore, both industry and academia seek solutions to automate the generation of stimuli to reach all the functionalities of interest with less human effort and in less time. In this paper, several approaches inspired by genetic algorithms were developed and tested using three different designs. In all situations, the percentage of stimulus sets generated using well-performing genetic algorithms approaches was higher than the values that resulted when random simulations were employed. In addition, in most cases the genetic algorithm approach reached a higher coverage value per test compared to the random simulation outcome. The results confirmed that in many cases genetic algorithms can outperform constrained random generation of stimuli, that is employed in the classical way of doing verification, considering coverage fulfillment level per verification test.

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Section: Functional Verification: Implementation and Challengesmentioning

confidence: 99%

Coverage Fulfillment Automation in Hardware Functional Verification Using Genetic Algorithms

Danciu

Dinu

2022

Applied Sciences

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“…Coverage is the most important metric of the verification process and is intensely collected during each test run in the traditional approach [ 14 ]. However, collecting coverage makes simulations run slower.…”

Section: Literature Reviewmentioning

confidence: 99%

Cost-Efficient Approaches for Fulfillment of Functional Coverage during Verification of Digital Designs

2022

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Digital integrated circuits play an important role in the development of new information technologies and support Industry 4.0 from a hardware point of view. There is great pressure on electronics companies to reduce the time-to-market for product development as much as possible. The most time-consuming stage in hardware development is functional verification. As a result, many industry and academic stakeholders are investing in automating this crucial step in electronics production. The present work aims to automate the functional verification process by means of genetic algorithms that are used for generating the relevant input stimuli for full simulation of digital design behavior. Two important aspects are pursued throughout the current work: the implementation of genetic algorithms must be time-worthy compared to the application of the classical constrained-driven generation and the verification process must be implemented using tools accessible to a wide range of practitioners. It is demonstrated that for complex designs, functional verification powered by the use of genetic algorithms can go beyond the classical method of performing verification, which is based on constrained-random stimulus generation. The currently proposed methods were able to generate several sets of highly performing stimuli compared to the constraint-random stimulus generation method, in a ratio ranging from 57:1 to 205:1. The performance of the proposed approaches is comparable to that of the well-known NSGA-II and SPEA2 algorithms.

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“…In [11], authors proposed using features in the e language along with universal verification methodology UVM [12] phasing to enable a DNN model learning from coverage results of a processor DUT. Coverage is dynamically read using Specman coverage API.…”

Section: Stimulus and Test Generationmentioning

confidence: 99%

“…Other attempts incorporated additional different ML models such as Markov models and inductive logic programming to reach a faster coverage convergence rate [6][7][8]. More recent research in the domain of stimulus and test generation used a combination of supervised and unsupervised ML models such as neural networks, random forest and support vector machines to reduce the amount of needed input iterations and testcases to reach the planned coverage goals [9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28]. In the scope of coverage collection, there are studies that show improvements in both the runtime of simulations that capture coverage and the percentage of coverage reached, when either a supervised or unsupervised ML model is used [29][30][31].…”

Section: Introductionmentioning

confidence: 99%

Survey on Machine Learning Algorithms Enhancing the Functional Verification Process

Ismail¹,

Ghany

2021

Electronics

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The continuing increase in functional requirements of modern hardware designs means the traditional functional verification process becomes inefficient in meeting the time-to-market goal with sufficient level of confidence in the design. Therefore, the need for enhancing the process is evident. Machine learning (ML) models proved to be valuable for automating major parts of the process, which have typically occupied the bandwidth of engineers; diverting them from adding new coverage metrics to make the designs more robust. Current research of deploying different (ML) models prove to be promising in areas such as stimulus constraining, test generation, coverage collection and bug detection and localization. An example of deploying artificial neural network (ANN) in test generation shows 24.5× speed up in functionally verifying a dual-core RISC processor specification. Another study demonstrates how k-means clustering can reduce redundancy of simulation trace dump of an AHB-to-WHISHBONE bridge by 21%, thus reducing the debugging effort by not having to inspect unnecessary waveforms. The surveyed work demonstrates a comprehensive overview of current (ML) models enhancing the functional verification process from which an insight of promising future research areas is inferred.

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Opportunities of using artificial intelligence in hardware verification

Cited by 9 publications

References 2 publications

Coverage Fulfillment Automation in Hardware Functional Verification Using Genetic Algorithms

Coverage Fulfillment Automation in Hardware Functional Verification Using Genetic Algorithms

Cost-Efficient Approaches for Fulfillment of Functional Coverage during Verification of Digital Designs

Survey on Machine Learning Algorithms Enhancing the Functional Verification Process

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