Operating system management of reconfigurable hardware computing systems

Rupnow, Kyle

doi:10.1109/fpt.2009.5377626

Cited by 5 publications

(3 citation statements)

References 3 publications

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“…A number of researchers have focused on providing OS support for reconfigurable hardware so as to provide a simple programming model to the user and effective run-time scheduling of hardware and software tasks [22], [23], [24], [25]. A technique to virtualize reconfigurable co-processors in high performance reconfigurable computing (HPRC) systems was presented in [26].…”

Section: Related Workmentioning

confidence: 99%

Microkernel hypervisor for a hybrid ARM-FPGA platform

Pham

Jain

Cui³

et al. 2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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Reconfigurable architectures have found use in a wide range of application domains, but mostly as static accelerators for computationally intensive functions. Commodity computing adoption has not taken off due primarily to design complexity challenges. Yet reconfigurable architectures offer significant advantages in terms of sharing hardware between distinct isolated tasks, under tight time constraints. Trends towards amalgamation of computing resources in the automotive and aviation domains have so far been limited to non-critical systems, because processor approaches suffer from a lack of predictability and isolation. Hybrid reconfigurable platforms may provide a promising solution to this, by allowing physically isolated access to hardware resources, and support for computationally demanding applications, but with improved programmability and management. We propose virtualized execution and management of software and hardware tasks using a microkernel-based hypervisor running on a commercial hybrid computing platform (the Xilinx Zynq). We demonstrate a framework based on the CODEZERO hypervisor, which has been modified to leverage the capabilities of the FPGA fabric. It supports discrete hardware accelerators, dynamically reconfigurable regions, and regions of virtual fabric, allowing for application isolation and simpler use of hardware resources. A case study demonstrating multiple independent (and isolated) software and hardware tasks is presented.

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Section: Related Workmentioning

confidence: 99%

Microkernel hypervisor for a hybrid ARM-FPGA platform

Pham

Jain

Cui³

et al. 2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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“…In an accelerator context, this concept of being able to modify the behaviour at runtime by swapping in and out different accelerators and reusing the FPGA resources for multiple tasks [45,46,47,48,49,50] is an advantage. A large application may need to be decomposed into several smaller hardware tasks, each of which is mapped to a temporal FPGA partition [51,52] and executed in a time multiplexed manner under the control of an operating system (OS) which normally runs on a host processor [51,52,53,54,55]. While such ideas have been explored in the past, modern hybrid FPGAs are the first commercial platforms to enable this move to a more software oriented view.…”

Section: The Gap Between Fpgas and Asics Is Shrinking With Each New Gmentioning

confidence: 99%

“…A number of researchers have focused on providing operating system (OS) support for FPGA hardware so as to provide a simple programming model to the user and effective run-time scheduling of hardware and software tasks [45,53,95,55].…”

Section: Communication Interfaces and Runtime Managementmentioning

confidence: 99%

Architecture centric coarse-grained FPGA overlays

Abhishek¹

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Coarse-grained FPGA overlays have emerged as one possible solution to make FPGAs more accessible to application developers who are accustomed to software API abstractions and fast development cycles. Existing overlay architectures offer a number of advantages for general purpose hardware acceleration because of software-like programmability, fast compilation, application portability, and improved design productivity, but at the cost of area and performance overheads due to limited consideration for the underlying FPGA architecture. This thesis explores coarse grained overlays designed using the flexible DSP48E1 primitive on Xilinx FPGAs, allowing pipelined execution of compute kernels at significantly higher throughput. We first evaluate an open source overlay architecture, DySER, mapped on the Xilinx Zynq device and show that DySER suffers from a significant area and performance overhead due to limited consideration for the underlying FPGA architecture. Next, we design and implement a more FPGA targeted overlay architecture that maximizes the peak performance and reduces the interconnect area overhead through the use of an array of DSP block based fully pipelined functional units and an island-style coarse-grained routing network. As the interconnect of the island-style overlay is still excessive, we next explore novel interconnect architectures to further reduce the interconnect area. We next develop DeCO, a cone shaped cluster of FUs, which shows 87% savings in LUT requirements compared to our island-style overlay, for a set of compute kernels. Our experimental evaluation shows that the proposed overlays exhibit frequencies close to the DSP theoretical limit and achieve high performance with significantly reduced area overheads. We also present a methodology for compiling high level language (C/OpenCL) descriptions of compute kernels onto DSP block based coarse-grained overlays. Our mapping flow provides a rapid, vendor independent mapping to the overlay, raising the abstraction level while also reducing compilation time significantly, hence addressing the design productivity issue.

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