OpenNVM: An open-sourced FPGA-based NVM controller for low level memory characterization

Zhang, Jie; Park, Gieseo; Shihab, Mustafa M.; Donofrio, David; Shalf, John

doi:10.1109/iccd.2015.7357179

Cited by 19 publications

(9 citation statements)

References 17 publications

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“…For instance, the authors in [30] found that the effective write latency can reach up to several milliseconds. Accordingly, we perform a sensitivity study to estimate the impact of various write latencies of flash memory on the execution time of the memory extension, compared to that of the PCM-based memory extension.…”

Section: Sensitivity Studymentioning

confidence: 98%

Write-Aware Management of NVM-based Memory Extensions

Awad

Blagodurov

Solihin

2016

Proceedings of the 2016 International Conference on Supercomputing

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Emerging Non-Volatile Memory (NVM) technologies, such as 3D XPoint, are expected to be in production as early as 2016. Emerging NVMs are very attractive for several reasons. First, they are non-volatile and hence incur no refresh power. Second, they are dense and promising for scaling down further. Finally, they are fast and have latencies comparable to DRAM. On the other side, using emerging NVMs as direct replacement for DRAM as the main memory is challenging. Compared to DRAM, emerging NVMs can endure a very limited number of writes per cell. Furthermore, their write latency is typically much slower and more energy consuming than DRAM, e.g., Phase Change Memory (PCM) writes are multiple of times slower than that of DRAM. An important use case for emerging NVMs is using them as fast memory extensions. Memory extensions are hidden from programmers and managed by the Operating System (OS). Any access to pages held in the memory extension will cause a page fault. Later, the memory manager moves the faulting page to DRAM and maps the page. While similar in concept to the swap file, memory extensions bypass the file system. Furthermore, memory extensions are dedicated for being used as memory and hence avoid contention with the file system.In this paper, we emulate an NVM-based memory extension and study its impact on performance on a real system. We also study how to improve its performance using OSlevel prefetching. We show the importance of having the system software and the NVM controller work in concert for reducing the number of writes. Our best scheme where the system software and the NVM controller work in concert could reduce the number of writes to only 5% of the original baseline (increasing its lifetime by 20×).

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Section: Sensitivity Studymentioning

confidence: 98%

Write-Aware Management of NVM-based Memory Extensions

Awad

Blagodurov

Solihin

2016

Proceedings of the 2016 International Conference on Supercomputing

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“…On the other hand, to enable dual routes for swap function, one laser light stream needs to carry two pieces of data, one from memory requests and another from data migration requests. To this end, we leverage a write-once memory (WOM) coding [71]. By using WOM coding, Ohm-GPU can modulate two different 2-bit data in a 3-bit laser light signal.…”

Section: Optical Network Infrastructurementioning

confidence: 99%

Ohm-GPU: Integrating New Optical Network and Heterogeneous Memory into GPU Multi-Processors

Zhang,

Jung

2021

Preprint

Self Cite

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Traditional graphics processing units (GPUs) suffer from the low memory capacity and demand for high memory bandwidth. To address these challenges, we propose Ohm-GPU, a new optical network based heterogeneous memory design for GPUs. Specifically, Ohm-GPU can expand the memory capacity by combing a set of high-density 3D XPoint and DRAM modules as heterogeneous memory. To prevent memory channels from throttling throughput of GPU memory system, Ohm-GPU replaces the electrical lanes in the traditional memory channel with a high-performance optical network. However, the hybrid memory can introduce frequent data migrations between DRAM and 3D XPoint, which can unfortunately occupy the memory channel and increase the optical network traffic. To prevent the intensive data migrations from blocking normal memory services, Ohm-GPU revises the existing memory controller and designs a new optical network infrastructure, which enables the memory channel to serve the data migrations and memory requests, in parallel. Our evaluation results reveal that Ohm-GPU can improve the performance by 181% and 27%, compared to a DRAM-based GPU memory system and the baseline optical network based heterogeneous memory system, respectively.

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“…However, it incurs severe problems especially for low-level flash in SSD arrays. Since flash does not allow an overwrite to a physical block (without erasing), SSD firmware in practice forwards the incoming write to another reserved block, which was erased in advance, and invalids the overwritten data by remapping the corresponding address with new one [32], [33]. Therefore, the increased amount of data that needs to be written to the underlying flash shortens the life time of SSD regardless of the storage overhead of the erasure coding.…”

Section: B Summary Of In-depth Analysesmentioning

confidence: 99%

Exploring Fault-Tolerant Erasure Codes for Scalable All-Flash Array Clusters

Koh

Zhang

Kwon

et al. 2019

IEEE Trans. Parallel Distrib. Syst.

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Large-scale systems with all-flash arrays have become increasingly common in many computing segments. To make such systems resilient, we can adopt erasure coding such as Reed-Solomon (RS) code as an alternative to replication because erasure coding incurs a significantly lower storage overhead than replication. To understand the impact of using erasure coding on the system performance and other system aspects such as CPU utilization and network traffic, we build a storage cluster that consists of approximately 100 processor cores with more than 50 high-performance solid-state drives (SSDs), and evaluate the cluster with a popular open-source distributed parallel file system, called Ceph. Specifically, we analyze the behaviors of a system adopting erasure coding from the following five viewpoints, and compare with those of another system using replication: (1) storage system I/O performance; (2) computing and software overheads; (3) I/O amplification; (4) network traffic among storage nodes, and (5) impact of physical data layout on performance of RS-coded SSD arrays. For all these analyses, we examine two representative RS configurations, used by Google file systems, and compare them with triple replication employed by a typical parallel file system as a default fault tolerance mechanism. Lastly, we collect 96 block-level traces from the cluster and release them to the public domain for the use of other researchers.

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OpenNVM: An open-sourced FPGA-based NVM controller for low level memory characterization

Cited by 19 publications

References 17 publications

Write-Aware Management of NVM-based Memory Extensions

Write-Aware Management of NVM-based Memory Extensions

Ohm-GPU: Integrating New Optical Network and Heterogeneous Memory into GPU Multi-Processors

Exploring Fault-Tolerant Erasure Codes for Scalable All-Flash Array Clusters

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