OpenMP on the Low-Power TI Keystone II ARM/DSP System-on-Chip

Stotzer, Eric; Jayaraj, Ajay; Ali, Muhammad Yasir; Friedmann, Arnon; Mitra, Gaurav; Rendell, Alistair P.; Lintault, Ian

doi:10.1007/978-3-642-40698-0_9

Cited by 30 publications

(29 citation statements)

References 19 publications

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“…Use of low power ARM based SoC processors [13] and manycore accelerators such as the TI C66X DSP [14], [15] for high performance computing are also of increasing interest. A comparison of some of these systems is shown in The closest related work is that of Mattson et al [7].…”

Section: Systemsmentioning

confidence: 99%

Programming the Adapteva Epiphany 64-Core Network-on-Chip Coprocessor

Varghese

Edwards

Mitra

et al. 2014

2014 IEEE International Parallel &Amp; Distributed Processing Symposium Workshops

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Abstract-In the construction of exascale computing systems energy efficiency and power consumption are two of the major challenges. Low-power high performance embedded systems are of increasing interest as building blocks for large scale highperformance systems. However, extracting maximum performance out of such systems presents many challenges. Various aspects from the hardware architecture to the programming models used need to be explored. The Epiphany architecture integrates low-power RISC cores on a 2D mesh network and promises up to 70 GFLOPS/Watt of processing efficiency. However, with just 32 KB of memory per eCore for storing both data and code, and only low level inter-core communication support, programming the Epiphany system presents several challenges. In this paper we evaluate the performance of the Epiphany system for a variety of basic compute and communication operations. Guided by this data we explore strategies for implementing scientific applications on memory constrained low-powered devices such as the Epiphany. With future systems expected to house thousands of cores in a single chip, the merits of such architectures as a path to exascale is compared to other competing systems.

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Section: Systemsmentioning

confidence: 99%

Programming the Adapteva Epiphany 64-Core Network-on-Chip Coprocessor

Varghese

Edwards

Mitra

et al. 2014

2014 IEEE International Parallel &Amp; Distributed Processing Symposium Workshops

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“…RTEs for embedded parallel accelerators typically sit on top of hardware abstraction layers (HAL) [18] [19] [20] that expose low-level APIs to use bare iron resources. While designing a RTE with such a tight coupling to hardware resources enables very low overheads, it does not immediately allow the co-existence of multiple RTE, as hardware resources are physically identified.…”

Section: Acrm: the Multi-programming Model Multi-offload Pmca Managermentioning

confidence: 99%

Runtime Support for Multiple Offload-Based Programming Models on Clustered Manycore Accelerators

Capotondi¹,

Marongiu²,

Benini³

2018

IEEE Trans. Emerg. Topics Comput.

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Heterogeneous systems coupling a main host processor with one or more manycore accelerators are being adopted virtually at every scale to achieve ever-increasing GOps/Watt targets. The increased hardware complexity of such systems is paired at the application level by a growing number of applications concurrently running on the system. Techniques that enable efficient accelerator resources sharing, supporting multiple programming models will thus be increasingly important for future heterogeneous SoCs. In this paper we present a runtime system for a cluster-based manycore accelerator, optimized for the concurrent execution of offloaded computation kernels from different programming models. The runtime supports spatial partitioning, where clusters can be grouped into several virtual accelerator instances. Our runtime design is modular and relies on a generic component for resource (cluster) scheduling, plus specialized components which deploy generic offload requests into the target programming model semantics. We evaluate the proposed runtime system on two real heterogeneous systems, focusing on two concrete use cases: i) single-user, multi-application high-end embedded systems and ii) multi-user, multi-workload low-power microservers. In the first case, our approach achieves 93% efficiency in terms of available accelerator resource exploitation. In the second case, our support allows 47% performance improvement compared to single-programming model systems.

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“…Table I shows the array µi for each of the tasks shown in Figure 1 with m = 4. For example, the worst-case workload µ4 [2] occurs when NPRs v4,3 and v4,4 execute in parallel, with an overall impact of 9 time units. τ2 has a maximum parallelism of 2, so µ2 [3] and µ2 [4] are equal to 0.…”

Section: Definitionmentioning

confidence: 99%

“…The algorithm takes as input the DAG of task τi, the topological order 2 of Gi, and, for each node vi,j, the sets: (1) SIBLING(vi,j), which contains the nodes which have a common predecessor with 2 A topological order is such that if there is an edge from u to v in the DAG, then u appears before v in the topological order. A topological order can be easily computed in time linear in the size of the DAG [23].…”

Section: )mentioning

confidence: 99%

See 1 more Smart Citation

Response-Time Analysis of DAG Tasks under Fixed Priority Scheduling with Limited Preemptions

Serrano

Melani

Bertogna

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Limited preemptive (LP) scheduling has been demonstrated to effectively improve the schedulability of fully preemptive (FP) and fully non-preemptive (FNP) paradigms. On one side, LP reduces the preemption related overheads of FP; on the other side, it restricts the blocking effects of FNP. However, LP has been applied to multi-core scenarios only when completely sequential task systems are considered. This paper extends the current state-of-the-art response time analysis for global fixed priority scheduling with fixed preemption points by deriving a new response time analysis for DAG-based task-sets.

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OpenMP on the Low-Power TI Keystone II ARM/DSP System-on-Chip

Cited by 30 publications

References 19 publications

Programming the Adapteva Epiphany 64-Core Network-on-Chip Coprocessor

Programming the Adapteva Epiphany 64-Core Network-on-Chip Coprocessor

Runtime Support for Multiple Offload-Based Programming Models on Clustered Manycore Accelerators

Response-Time Analysis of DAG Tasks under Fixed Priority Scheduling with Limited Preemptions

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