Open-Source NoC-Based Many-Core for Evaluating Hardware Trojan Detection Methods

Weber, Iacana; Marchezan, Geaninne; Caimi, Luciano L.; Marcon, César; Moraes, Fernando

doi:10.1109/iscas45731.2020.9180578

Cited by 4 publications

(4 citation statements)

References 19 publications

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“…The authors in [18], implement a detection algorithm that detects changes in traffic communication to identify hostile IC's in the NOC. [19] has the authors make and subvert three types of trojan attacks. Packet Duplication, application blocking, and misrouting.…”

Section: Related Workmentioning

confidence: 99%

Address Obfuscation to Protect against Hardware Trojans in Network-on-Chips

Mountford,

Dhavlle,

Tevebaugh

et al. 2023

JLPEA

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In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware Trojan (HT) being injected into a system is particularly prevalent due to the increase in third-party manufacturers for system-on-chip (SoC) designs. With a local injection of an HT in an SoC, an adversary can gain access to information about applications running on the system by revealing specific communications of the SoC, and the network-on-chip (NoC) as a whole. This heavily compromises the system and gives information to the attacker, which can lead to more tailored, compromising attacks. In this paper, we demonstrate an HT that exploits communication patterns inside an SoC to reveal applications that are running on an NoC with multi/many-core processors. This is performed by leaking packet counts, after which the attacker then uses machine learning techniques to identify applications running on processors, and the SoC as a whole. We also propose a LUT-based obfuscation technique to limit the information available to the hardware Trojan. Our results indicate that this obfuscation method can reduce the accuracy of this attack from 99% to <8% in multi/many-core systems.

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Section: Related Workmentioning

confidence: 99%

Address Obfuscation to Protect against Hardware Trojans in Network-on-Chips

Mountford,

Dhavlle,

Tevebaugh

et al. 2023

JLPEA

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“…The goal of using this peripheral is to inject controlled traffic into the system to emulate attacks. The second mechanism is an HT circuit (based on [29]) connected to routers. The HT trigger may be a malicious application or a given condition (e.g., time-triggered HT) that can duplicate, misroute, or block flows.…”

Section: Security Analysis and Costsmentioning

confidence: 99%

A Comprehensive Framework for Systemic Security Management in NoC-Based Many-Cores

Faccenda,

Comarú,

Caimi

et al. 2023

IEEE Access

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Many-core Systems-on-Chip (MCSoC) are increasingly used in various applications domains such as high-performance computing, embedded systems, and Internet of Things devices. As MCSoCs permeate various industries and applications, the potential consequences of security issues are becoming increasingly severe. Therefore, security is a fundamental design constraint, addressing vulnerabilities and protecting valuable data from threats. This requires the development of robust security mechanisms and countermeasures against potential threats. The reviewed works on security for MCSoCs addressed frameworks and mechanisms to treat different security threats. Despite these proposals, the integration of security mechanisms still needs to be improved, enabling a security manager to make decisions using monitoring data for mitigating threats more effectively. This integration is the primary goal of our work, aiming to create a comprehensive framework for security management. The framework adopts a Monitoring-Detection-Countermeasure loop. A distributed monitoring infrastructure detects suspicious behaviors, generating warnings to different system actors. These actors decide the warning severity, firing security countermeasures. Countermeasures may be local (e.g., discarding a packet) or taken at the system level (e.g., aborting a malicious application). The results use an MCSoC modeled at the RTL level, providing accuracy at the clock cycle (cc) level. Five different attack scenarios are evaluated, showing that the gap between attack detection and countermeasure takes less than one millisecond (15,000 cc at 100 MHz). The area overhead in the communication infrastructure corresponds to 48.8%. These results show that the framework can effectively manage the system's security while maintaining the performance of the applications.INDEX TERMS Countermeasures, Monitoring, NoC-based Many-cores, Security Framework.

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“…Each normal packet generated by the transmitter in the network is routed through a series of intermediate nodes before reaching the receiver. However, some of these intermediate nodes may be embedded with hardware Trojans (HTs), which can keep a local copy of any packet [14], or use hardwaresupported debugging, such as the trace buffer [9], to export traffic traces to an unintended external analyzer. Either way there is a great danger of information leakage.…”

Section: A Threat Modelmentioning

confidence: 99%

“…Unfortunately, a manycore chip's network-on-chip (NoC) is perceived to be one of the most vulnerable spots in the security chain [25]. To reduce the time to market, a chip's NoC is often adopted from a third party vendor and there has been a great concern that it might have been compromised by hardware Trojans (HTs) [14], [49]. Unfortunately, completely removing all these hardware Trojans, particularly those conditionally triggered and switched on for a short duration of time, cannot be guaranteed at offline circuit testing stage.…”

Section: Introductionmentioning

confidence: 99%

Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays

Wang

Jiang

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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As the network-on-chip (NoC) integrated into an SoC design can come from an untrusted third party, there is a growing risk that data integrity and security get compromised when supposedly sensitive data flows through such an untrusted NoC. We thus introduce a new method that can ensure secure and secret data transmission over such an untrusted NoC. Essentially, the proposed scheme relies on encoding binary data as delays between packets travelling across the source and destination pair. The maximum data transmission rate of this inter-packet-delay (IPD) based communication channel can be determined from the analytical model developed in this paper. To further improve the undetectability and robustness of the proposed data transmission scheme, a new block coding method and communication protocol are also proposed. Experimental results show that the proposed IPD-based method can achieve a packet error rate (PER) of as low as 0.3% and an effective throughput of 2.3 × 10 5 bps, outperforming the methods of thermal covert channel, cache covert channel, and circuit-based encryption, and thus is suitable for secure data transmission in unsecure systems.

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Open-Source NoC-Based Many-Core for Evaluating Hardware Trojan Detection Methods

Cited by 4 publications

References 19 publications

Address Obfuscation to Protect against Hardware Trojans in Network-on-Chips

Address Obfuscation to Protect against Hardware Trojans in Network-on-Chips

A Comprehensive Framework for Systemic Security Management in NoC-Based Many-Cores

Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays

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