ONNC-Based Software Development Platform for Configurable NVDLA Designs

Lin, Wei-Fen; Hsieh, Chia-Lung; Chou, Cheng-Yi

doi:10.1109/vlsi-dat.2019.8741778

Cited by 5 publications

(2 citation statements)

References 1 publication

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“…This section discusses the proposed CortexM backend for the ONNC compiler by comparing it with other backends such as the C, NVIDIA Deep Learning Accelerator (NVDLA) [27], and LLVM backends. First, measured by the number of lines of source code, the proposed implementation is less complex than the others.…”

Section: Discussionmentioning

confidence: 99%

Constructing an AI Compiler for ARM Cortex-M Devices

Chang¹,

Hoang²

2023

Computer Systems Science and Engineering

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The diversity of software and hardware forces programmers to spend a great deal of time optimizing their source code, which often requires specific treatment for each platform. The problem becomes critical on embedded devices, where computational and memory resources are strictly constrained. Compilers play an essential role in deploying source code on a target device through the backend. In this work, a novel backend for the Open Neural Network Compiler (ONNC) is proposed, which exploits machine learning to optimize code for the ARM Cortex-M device. The backend requires minimal changes to Open Neural Network Exchange (ONNX) models. Several novel optimization techniques are also incorporated in the backend, such as quantizing the ONNX model's weight and automatically tuning the dimensions of operators in computations. The performance of the proposed framework is evaluated for two applications: handwritten digit recognition on the Modified National Institute of Standards and Technology (MNIST) dataset and model, and image classification on the Canadian Institute For Advanced Research and 10 (CIFAR-10) dataset with the AlexNet-Light model. The system achieves 98.90% and 90.55% accuracy for handwritten digit recognition and image classification, respectively. Furthermore, the proposed architecture is significantly more lightweight than other state-of-theart models in terms of both computation time and generated source code complexity. From the system perspective, this work provides a novel approach to deploying direct computations from the available ONNX models to target devices by optimizing compilers while maintaining high efficiency in accuracy performance.

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Section: Discussionmentioning

confidence: 99%

Constructing an AI Compiler for ARM Cortex-M Devices

Chang¹,

Hoang²

2023

Computer Systems Science and Engineering

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“…Its maximum clock is 1088 MHz and the list of supported algorithms includes Stereo Disparity Estimator, KLT Bounding Box Tracker, Gaussian Pyramid Generator, Image Convolver, Separable Image Convolver, Box Image Filter and Gaussian Image Filter. The DLA is an accelerator capable of efficiently performing neural network inference[21],[22] over network topologies featuring convolution, deconvolution, pooling, fully connected, normalization, scaling and element-wise layers over a limited set of data precision. Supported activation functions are ReLU, Sigmoid and Hyperbolic Tangent.…”

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confidence: 99%

Contending memory in heterogeneous SoCs: Evolution in NVIDIA Tegra embedded platforms

Capodieci

Cavicchioli

Olmedo

et al. 2020

2020 IEEE 26th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

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Modern embedded platforms are known to be constrained by size, weight and power (SWaP) requirements. In such contexts, achieving the desired performance-per-watt target calls for increasing the number of processors rather than ramping up their voltage and frequency. Hence, generation after generation, modern heterogeneous System on Chips (SoC) present a higher number of cores within their CPU complexes as well as a wider variety of accelerators that leverages massively parallel compute architectures. Previous literature demonstrated that while increasing parallelism is theoretically optimal for improving on average performance, shared memory hierarchies (i.e. caches and system DRAM) act as a bottleneck by exposing the platform processors to severe contention on memory accesses, hence dramatically impacting performance and timing predictability. In this work we characterize how subsequent generations of embedded platforms from the NVIDIA Tegra family balanced the increasing parallelism of each platform's processors with the consequent higher potential on memory interference. We also present an open-source software for generating test scenarios aimed at measuring memory contention in highly heterogeneous SoCs.

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