Online Fault Tolerance for FPGA Logic Blocks

Emmert, John M.; Stroud, Charles E.; Abramovici, M.

doi:10.1109/tvlsi.2007.891102

Cited by 71 publications

(29 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Hatori et al (1993) and Caponetto et al (2007), the authors developed a switch matrix network. Emmert et al (2007), the authors proposed a technique that uses a spare or an unused resource for fault tolerance. This FT depends on the routability and the available unused resources.…”

Section: Related Researchmentioning

confidence: 99%

Reconfiguring Evolved Circuits Using Controller: A Real Time Approach

Krishna¹

2014

Journal of Computer Science

View full text Add to dashboard Cite

FPGA is a device that contains a matrix of reconfigurable gate arrays that can implement different complex functions and also vary structurally. In this study, a novel method of reconfigurable circuit switching action is done with the help of a controller. BPSK Modulation application is chosen to demonstrate the reconfigurable action. When an event occurs the context/core switching is done at both input and output and also preserving the structural and functional relationship. The reconfiguration ability of FPGA with an embedded core performing the switching in real time is the focus of this study. A controller running on Linux platform is used along with the FPGA core. In this study, we propose a real time approach for reconfiguring evolved circuits using controller. It has an adaptive hardware that can continuously change in response to the input data and there by perform reconfiguration. Here the reconfiguration process is achieved by using a real time controller which gives a command to the FPGA core (ALTERA (Cypress processor)) for reconfiguration.

show abstract

Section: Related Researchmentioning

confidence: 99%

Reconfiguring Evolved Circuits Using Controller: A Real Time Approach

Krishna¹

2014

Journal of Computer Science

View full text Add to dashboard Cite

show abstract

“…Using partial dynamic reconfiguration of FPGAs, the test reconfiguration can be conducted by an external [24] or embedded processor during runtime [25,26]. Access to an internal high-bandwidth configuration port significantly reduces the time required for reconfiguration.…”

Section: State Of the Art Fpga Testmentioning

confidence: 99%

Transparent structural online test for reconfigurable systems

Abdelfattah

Bauer

Braun

et al. 2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

View full text Add to dashboard Cite

FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing.In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application.

show abstract

“…Ambramovici et al [16]- [18] have demonstrated how self testing of small portions of a circuit can be carried out simultaneously with normal functioning of other parts. In [17], [18], a Self Testing Area, so called STAR, is first offloaded by reconfiguring its functionality on another area so that normal functioning is not affected at all, thus enabling online self testing using BIST (Built In Self Testing).…”

Section: Related Workmentioning

confidence: 99%

“…In [17], [18], a Self Testing Area, so called STAR, is first offloaded by reconfiguring its functionality on another area so that normal functioning is not affected at all, thus enabling online self testing using BIST (Built In Self Testing).…”

Section: Related Workmentioning

confidence: 99%

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

Sharma¹,

Chakraverty²

2012

IJET

View full text Add to dashboard Cite

Abstract-Thedynamically reconfigurable Field Programmable Gate Arrays (FPGAs) are most frequently employed for developing adaptive embedded systems. They are also being increasingly used as co-processors in high performance computing applications. For these systems to be fielded in harsh environments such as those encountered in space, extra-terrestrial locations and regions of extreme conditions on the earth, one must adopt fault tolerant design techniques to ensure uninterrupted and reliable operation despite the occurrence of faults. Commercial Off-the-Shelf (COTS) FPGA components offer a cost effective design trajectory where the designer can choose among a rich variety of FT approaches and techniques. This paper compares the various FT techniques and proposes a novel method in which these techniques can work together to provide a synergetic approach for fault tolerant FPGA design.

show abstract

Online Fault Tolerance for FPGA Logic Blocks

Cited by 71 publications

References 20 publications

Reconfiguring Evolved Circuits Using Controller: A Real Time Approach

Reconfiguring Evolved Circuits Using Controller: A Real Time Approach

Transparent structural online test for reconfigurable systems

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

Contact Info

Product

Resources

About