Online check and recovery techniques for dependable embedded processors

Pflanz, Matthias; Vierhaus, Heinrich Theodor

doi:10.1109/40.958697

Cited by 21 publications

(13 citation statements)

References 9 publications

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“…A SEU on the configuration memory may cause permanent faults on the "combinational logic" of the CPU. The only configuration of the fault-tolerant LEON architecture that provides greater protection against this kind of faults is the master-checker mode [15], [1] (using 2 CPUs), which has a 100% area overhead, thus its use is limited to applications extremely demanding in terms of error detection.…”

Section: A Processor Architecture Adaptationmentioning

confidence: 99%

“…This simple scheme has been used because of its straightforward implementation and acceptable area overhead. In a more sophisticated architecture a Berger code based solution could be adopted, as suggested in [1].…”

Section: A Processor Architecture Adaptationmentioning

confidence: 99%

“…Although the symptoms of transient or permanent faults on FPGAs can be categorized in component and control faults as proposed in [1], their source can be different and more complex to discover than on traditional ASICs. In a FPGA design, a permanent fault does not necessarily identify a damaged circuit; it can be generated by a bit-flipping of the FPGA configuration memory.…”

Section: Introductionmentioning

confidence: 99%

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Microprocessor fault-tolerance via on-the-fly partial reconfiguration

Carlo

Miele

Prinetto

et al. 2010

2010 15th IEEE European Test Symposium

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This paper presents a novel approach to exploit FPGA dynamic partial reconfiguration to improve the fault tolerance of complex microprocessor-based systems, with no need to statically reserve area to host redundant components. The proposed method not only improves the survivability of the system by allowing the online replacement of defective key parts of the processor, but also provides performance graceful degradation by executing in software the tasks that were executed in hardware before a fault and the subsequent reconfiguration happened. The advantage of the proposed approach is that thanks to a hardware hypervisor, the CPU is totally unaware of the reconfiguration happening in real-time, and there's no dependency on the CPU to perform it. As proof of concept a design using this idea has been developed, using the LEON3 open-source processor, synthesized on a Virtex 4 FPGA.

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Section: A Processor Architecture Adaptationmentioning

confidence: 99%

Section: A Processor Architecture Adaptationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Microprocessor fault-tolerance via on-the-fly partial reconfiguration

Carlo

Miele

Prinetto

et al. 2010

2010 15th IEEE European Test Symposium

View full text Add to dashboard Cite

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“…Unfortunately, even with carefully selected functional tests, there will always be a number of special test cases, which are not covered explicitly. For example, processor control logic will usually produce a number of "don't care" cases with respect to control signals [20,21]. Therefore a comprehensive test procedure "in the field" requires structures known from scan test or logic BIST to achieve a reasonably high fault coverage in critical structures such as control logic.…”

Section: Introductionmentioning

confidence: 99%

A hierarchical self test scheme for SoCs

Kretzschmar¹,

Galke²,

Vierhaus³

Proceedings. 10th IEEE International on-Line Testing Symposium

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Complex systems on a chip (SoCs) suffer from a couple of test related problems. In almost any case they contain processor devices and complex on-chip networks that need to be tested under heavily restricted access from the outside. Today multi-processor SoCs (MP-SoCs) are becoming the rule rather than the exception and many SoCs consist of heterogeneous multi-processor networks that are partly asynchronous. Therefore testing processor structures (logic, busses, memory) is an essential part of the problem. For SoCs in safety-critical applications, selftest functions that work independently from external tester devices are becoming a must. This paper presents a new concept for a tester-independent "bottom up" self-test strategy for multi-processor SoCs.

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“…To meet the high safety requirements of future applications -as demanded in the European standard EN 61508, for instance -in spite of the increasing rate of transient errors [1], [2] that is predicted to result from reduced voltage levels and shrinking feature size [3], the microprocessors have to be equipped with powerful mechanisms for error detection and error handling. While it is relatively easy to protect memory or communication interfaces by means of coding techniques, e.g., the core is more difficult to protect (see [4], [5], [6], [7], [8], [9] for example). One attractive generic solution in this context is a dual-core (master/checker, e.g.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Generic Dual-Core Architecture

Kottke¹,

Steininger

International Conference on Dependable Systems and Networks (DSN'06)

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Abstract-In this paper we propose a generic frame for the implementation of a dual-core processor with two modes of operation. One is the safety mode that allows to run the two cores in lock step in a classical master/checker fashion. A clock delay of 1.5 clock cycles between master and checker establishes the temporal redundancy to minimize the potential for common mode faults. The second operation mode allows a parallel execution of different instruction streams on the two cores in a multiprocessor fashion. The possibility to dynamically switch between the two modes allows for an efficient utilization of the duplicated core.We propose an implementation of such a generic frame that can be applied in conjunction with virtually any standard processor core. Also we perform a systematic failure analysis for the safety mode and the mode switching procedure. Experimental fault injection confirms that our reconfigurable architecture indeed provides the same fail safe properties as the classical master/checker architecture.

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Online check and recovery techniques for dependable embedded processors

Cited by 21 publications

References 9 publications

Microprocessor fault-tolerance via on-the-fly partial reconfiguration

Microprocessor fault-tolerance via on-the-fly partial reconfiguration

A hierarchical self test scheme for SoCs

A Reconfigurable Generic Dual-Core Architecture

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