OneChip: an FPGA processor with reconfigurable logic

Chow,

doi:10.1109/fpga.1996.564773

Cited by 174 publications

(87 citation statements)

References 13 publications

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“…With a maximum degree of parallelism and software flexibility, it ensures high performance in the implemented system which makes the evolution of embedded devices on FPGA. Thus, FPGA becomes a trade-off to application specific integrated circuit with reconfigurable feature [2]. Merging hardware and software design components to work as a single embedded system is challenging.…”

Section: Fpga and Integrated Environmentmentioning

confidence: 99%

Reconfigurable Fpga Based Soft-Core Processor for Simd Applications

Maheswari

Pattabiraman

Sharmila

2017

Asian J Pharm Clin Res

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Objective: The prospective need of SIMD (Single Instruction and Multiple Data) applications like video and image processing in single system requires greater flexibility in computation to deliver high quality real time data. This paper performs an analysis of FPGA (Field Programmable Gate Array) based high performance Reconfigurable OpenRISC1200 (ROR) soft-core processor for SIMD.Methods: The ROR1200 ensures performance improvement by data level parallelism executing SIMD instruction simultaneously in HPRC (High Performance Reconfigurable Computing) at reduced resource utilization through RRF (Reconfigurable Register File) with multiple core functionalities. This work aims at analyzing the functionality of the reconfigurable architecture, by illustrating the implementation of two different image processing operations such as image convolution and image quality improvement. The MAC (Multiply-Accumulate) unit of ROR1200 used to perform image convolution and execution unit with HPRC is used for image quality improvement.Result: With parallel execution in multi-core, the proposed processor improves image quality by doubling the frame rate up-to 60 fps (frames per second) with peak power consumption of 400mWatt. Thus the processor gives a significant computational cost of 12ms with a refresh rate of 60Hz and 1.29ns of MAC critical path delay.Conclusion:This FPGA based processor becomes a feasible solution for portable embedded SIMD based applications which need high performance at reduced power consumptions

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Section: Fpga and Integrated Environmentmentioning

confidence: 99%

Reconfigurable Fpga Based Soft-Core Processor for Simd Applications

Maheswari

Pattabiraman

Sharmila

2017

Asian J Pharm Clin Res

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“…Because of the tight coupling between the PFU and the base CPU, PRISC requires only a small amount of configurable hardware resources and minimizes communication costs. Other representatives of this class include CoMPARE [11] and OneChip [12], etc. CoMPARE explores the impact of multiple PFUs and can execute RISC instructions and customized instructions concurrently.…”

Section: Prior Workmentioning

confidence: 99%

Augmenting Modern Superscalar Architectures with Configurable Extended Instructions

Zhang

Martonosi

2000

Lecture Notes in Computer Science

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Abstract. The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, however, are limited by a need for generality and for streamlined implementation. The particular needs of one application are balanced against the needs of the full range of applications considered. For this reason, one can "design" a better instruction set when considering only a single application than when considering a general collection of applications. Configurable hardware gives us the opportunity to explore this option. This paper examines the potential for automatically identifying application-specific extended instructions and implementing them in programmable functional units based on configurable hardware. Adding fine-grained reconfigurable hardware to the datapath of an out-of-order issue superscalar processor allows 4-44% speedups on the MediaBench benchmarks [1]. As a key contribution of our work, we present a selective algorithm for choosing extended instructions to minimize reconfiguration costs within loops. Our selective algorithm constrains instruction choices so that significant speedups are achieved with as few as 4 moderately sized programmable functional units, typically containing less than 150 look-up tables each.

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“…The presence of repeaters means that adding some reconfigurable logic to these wires will only modestly impact their performance. Reconfiguration at this level leads to coarser-grained configurability than previous reconfigurabje architectures, most of which were at least in part based on FPGA implementations [11][12][13][14][15][16][17][18]. Compared to these systems, Smart Memories trades away some flexibility for lower overheads, more familiar programming models, and higher efficiency.…”

Section: Distribution Stateiv1emt Amentioning

confidence: 99%

Smart Memories: a modular reconfigurable architecture

Mai

Paaske

Jayasena

et al.

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201)

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Itends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general purpose designs. To address these conflicting requirements, we propose a modular reconfigurable architecture called Smart Memories, tai^eted at computing needs in the O.l^m technology generation. A Smart Memories chip is made up of many processing tiles, each containing local memory, local interconnect, and a processor core. For efficient computation under a wide class of possible applications, the memories, the wires, and the computational model can all be altered to match the applications. To show the applicability of this design, two very different machines at opposite ends of the architectural spectrum, the Imagine stream processor and the Hydra speculative multiprocessor, are mapped onto the Smart Memories computing substrate. Simulations of the mappings show that the Smart Memories architecture can successfully map these architectures with only modest performance degradation.

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OneChip: an FPGA processor with reconfigurable logic

Cited by 174 publications

References 13 publications

Reconfigurable Fpga Based Soft-Core Processor for Simd Applications

Reconfigurable Fpga Based Soft-Core Processor for Simd Applications

Augmenting Modern Superscalar Architectures with Configurable Extended Instructions

Smart Memories: a modular reconfigurable architecture

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