On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs

Kinseher, Josef; Zordan, Leonardo B.; Polian, Ilia

doi:10.1109/ats.2015.18

Cited by 1 publication

(2 citation statements)

References 16 publications

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“…The algorithm performs the operation by using different backgrounds of data to increase the coverage of faults [5]. First, the memory array is initialized with the background data.…”

Section:  Issn: 2088-8708mentioning

confidence: 99%

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Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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Newer defects in memories arising from shrinking manufacturing technologies demand improved memory testing methodologies. The percentage of memories on chips continues to rise. With shrinking technologies (10 nm up to 1.8 nm), the structure of memories is becoming denser. Due to the dense structure and significant portion of a chip, the nanometer memories are highly susceptible to defects. High-frequency specifications, the complexity of internal connections, and the process variation due to newer manufacturing technology further increased the probability of the physical failure of memories to a great extent. Memories need to be defect-free for the chip to operate successfully. Therefore, testing embedded memories has become crucial and is taking significant test costs. Researchers have proposed multiple approaches considering these factors to test the nanometer memories. They include using new fault models, march algorithms, memory built-in self-test (MBIST) architectures, and validation strategies. This paper surveys the methodologies presented in recent times. It discusses the core principles used in them, along with benefits. Finally, it discusses key opens in each and offers the scope for future research.

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“…The algorithm performs the operation by using different backgrounds of data to increase the coverage of faults [5]. First, the memory array is initialized with the background data.…”

Section:  Issn: 2088-8708mentioning

confidence: 99%

“…The correctness of the operation must be checked whenever a new algorithm is developed. Kinseher et al [5] presented a flow to perform this. First, the algorithm is specified in a higher-level language.…”

Section: Algorithm Verificationmentioning

confidence: 99%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

View full text Add to dashboard Cite

show abstract

On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs

Cited by 1 publication

References 16 publications

Testing nanometer memories: a review of architectures, applications, and challenges

Testing nanometer memories: a review of architectures, applications, and challenges

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