On the Test and Mitigation of Malfunctions in Low-Power SRAMs

Zordan, L. H. Bonet; Bosio, Alberto; Dilillo, Luigi; Girard, Patrick; Virazel, Arnaud; Badereddine, N.

doi:10.1007/s10836-014-5479-z

Cited by 1 publication

(11 citation statements)

References 13 publications

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“…It is important to note that, in figure 3, resistances Df1 to Df6 (highlighted in red) are resistive-open defects that do not occur in a defect-free PM control logic. Such defects have been deeply analyzed in [7].…”

Section: Power Modesmentioning

confidence: 99%

“…an SRAM) to reduce the overall power noise on the system, during the WU phase. All the details are available in [7]. PM control logic ensures the expected activation order by controlling the falling transition of signals connected to the gate of transistors into PS segments during the WU phase, which is described as follows.…”

Section: Power Mode Control Logicmentioning

confidence: 99%

“…The complete defect analysis has been carried out in [7]. In the following we report the summary of the defect injection campaign for the sake of readability.…”

Section: Resistive-open Defects In the Pm Control Logicmentioning

confidence: 99%

“…The impacts of such effect are summarized in Table 1 from a qualitative point of view. Once again, all the details are available in [7] for each defect and considering the WU phase from DS and PO modes. …”

Section: Resistive-open Defects In the Pm Control Logicmentioning

confidence: 99%

“…In a previous work [7] we targeted the power-gating mechanisms. More specifically, we presented extensive electrical simulation results to show the impact of realistic defects that can affect the correct functioning of powergating circuitry.…”

Section: Introductionmentioning

confidence: 99%

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An effective BIST architecture for power-gating mechanisms in low-power SRAMs

Bosio

Dilillo

Girard

et al. 2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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In low-power SRAMs, power-gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting-off one or more memory blocks (core-cell array, address decoder, I/O logic, etc), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we present an efficient Built-InSelf-Test architecture targeting defects affecting powergating circuitry in low-power SRAMs. Experimental results show that the proposed solution improves the defect coverage and thus, it significantly increases the overall test quality compared to the state-of-the-art.

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Section: Power Modesmentioning

confidence: 99%

Section: Power Mode Control Logicmentioning

confidence: 99%

“…The complete defect analysis has been carried out in [7]. In the following we report the summary of the defect injection campaign for the sake of readability.…”

Section: Resistive-open Defects In the Pm Control Logicmentioning

confidence: 99%

Section: Resistive-open Defects In the Pm Control Logicmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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