On the SPEC-CPU 2017 opportunities for dynamic vectorization possibilities on PIM architectures

Abstract

Processing-In-Memory (PIM) devices usually implement vector instructions to efficiently utilize the large main memory bandwidth. One possible way to vectorize applications for such PIM systems is to convert CPU instructions into PIM vector instructions dynamically. In this work, we present a study on the feasibility of the dynamic conversion between these instructions for the Vector-In-Memory Architecture (VIMA). Our results show that 24 % of the loops from some SPEC-CPU 2017 applications are suitable for this conversion. Furthermore, we conclude that dynamic conversion mechanisms must to be able to efficiently deal with memory access conflicts, a problem present in 99 % of all possible conversions to VIMA.

A Simple AVX to PIM Vectorizer (SAPIVe)

“…Since VIMA does not have a set of registers, each of its instructions loads its operands and stores its result directly in memory addresses. Therefore, a VIMA instruction can be classified into one of the three types [27] identified in Figure 2, (a) a memory copy; (b) an operation on vector data, such as the sum of its elements with a scalar or; (c) an operation between two vectors, as a vector sum.…”