On the Reliability of In-Memory Computing: Impact of Temperature on Ferroelectric TCAM

Thomann, Simon; Li, Chao; Zhuo, Cheng; Prakash, Om; Yin, Xunzhao; Hu, Xiaobo Sharon; Amrouch, Hussam

doi:10.1109/vts50974.2021.9441038

Cited by 22 publications

(11 citation statements)

References 13 publications

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“…Details on our FinFET and FE calibrations are in [17], [18]. Note that to realize the effects of ferroelectric, a physicsbased model of FeFET [19] has been integrated within the BSIM-CMG, which is the industry standard compact model for the FinFET technology. In this work, the physical channel length is 21nm as provided in [20].…”

Section: A Fefinfet Device Modelingmentioning

confidence: 99%

Reliable Binarized Neural Networks on Unreliable Beyond Von-Neumann Architecture

Yayla

Thomann

Buschjäger

et al. 2022

IEEE Trans. Circuits Syst. I

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Specialized hardware accelerators beyond von-Neumann, that offer processing capability in where the data resides without moving it, become inevitable in data-centric computing. Emerging non-volatile memories, like Ferroelectric Field-Effect Transistor (FeFET), are able to build compact Logic-in-Memory (LiM). In this work, we investigate the probability of error (Perror) in FeFET-based XNOR LiM, demonstrating the new trade-off between the speed and reliability. Using our reliability model, we present how Binarized Neural Networks (BNNs) can be proactively trained in the presence of XNOR-induced errors towards obtaining robust BNNs at the design time. Furthermore, leveraging the trade-off between Perror and speed, we present a run-time adaptation technique, that selectively trades-off Perror and XNOR speed for every BNN layer. Our results demonstrate that when a small loss (e.g., 1%) in inference accuracy could be accepted, our design-time and run-time techniques provide error-resilient BNNs that exhibit 75% and 50% (FashionMNIST) and 38% and 24% (CIFAR10) XNOR speedups, respectively.

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Section: A Fefinfet Device Modelingmentioning

confidence: 99%

Reliable Binarized Neural Networks on Unreliable Beyond Von-Neumann Architecture

Yayla

Thomann

Buschjäger

et al. 2022

IEEE Trans. Circuits Syst. I

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“…Further, their error modeling was static and did not model the connection between different applications and incorrect Hamming distance computations. Ni et al and Thomann et al used a Fe-TCAM block to calculate the Hamming distance in a analog way similar to this work (Ni et al, 2019;Thomann et al, 2021). Both assumed a clocked self-referenced sense amplifier (CSRSA) translating the discharge current into the temporal domain and finally digital values, but no such circuit was presented.…”

Section: Related Workmentioning

confidence: 99%

“…In (Ni et al, 2019;Thomann et al, 2021) a similar approach is used as in Imani et al (2017) with a CSRSA, which also translates the discharge rate into the temporal domain. In these two works the conversion of the analog result to a digital one is not discussed.…”

Section: Comparison With Related Workmentioning

confidence: 99%

“…Additionally, FeFET is non-volatile, reducing energy demands and increasing compatibility with PiM on the transistor level. Recently, this compatibility has been utilized and TCAM-based PiM implementations have been proposed (Karam et al, 2015;Ni et al, 2019;Yin et al, 2019;Li et al, 2020;Thomann et al, 2021). However, most proposals using TCAM for PiM do not describe the conversion of the analog TCAM output into the digital domain (Ni et al, 2019;Thomann et al, 2021).…”

Section: Introductionmentioning

confidence: 99%

“…Recently, this compatibility has been utilized and TCAM-based PiM implementations have been proposed (Karam et al, 2015;Ni et al, 2019;Yin et al, 2019;Li et al, 2020;Thomann et al, 2021). However, most proposals using TCAM for PiM do not describe the conversion of the analog TCAM output into the digital domain (Ni et al, 2019;Thomann et al, 2021). If such a concept is described, the sensing or ADC circuitry consumes more transistors than the actual computation, reducing the efficiency Imani et al (2017).…”

Section: Introductionmentioning

confidence: 99%

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All-in-Memory Brain-Inspired Computing Using FeFET Synapses

et al. 2022

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The separation of computing units and memory in the computer architecture mandates energy-intensive data transfers creating the von Neumann bottleneck. This bottleneck is exposed at the application level by the steady growth of IoT and data-centric deep learning algorithms demanding extraordinary throughput. On the hardware level, analog Processing-in-Memory (PiM) schemes are used to build platforms that eliminate the compute-memory gap to overcome the von Neumann bottleneck. PiM can be efficiently implemented with ferroelectric transistors (FeFET), an emerging non-volatile memory technology. However, PiM and FeFET are heavily impacted by process variation, especially in sub 14 nm technology nodes, reducing the reliability and thus inducing errors. Brain-inspired Hyperdimensional Computing (HDC) is robust against such errors. Further, it is able to learn from very little data cutting energy-intensive transfers. Hence, HDC, in combination with PiM, tackles the von Neumann bottleneck at both levels. Nevertheless, the analog nature of PiM schemes necessitates the conversion of results to digital, which is often not considered. Yet, the conversion introduces large overheads and diminishes the PiM efficiency. In this paper, we propose an all-in-memory scheme performing computation and conversion at once, utilizing programmable FeFET synapses to build the comparator used for the conversion. Our experimental setup is first calibrated against Intel 14 nm FinFET technology for both transistor electrical characteristics and variability. Then, a physics-based model of ferroelectric is included to realize the Fe-FinFETs. Using this setup, we analyze the circuit’s susceptibility to process variation, derive a comprehensive error probability model, and inject it into the inference algorithm of HDC. The robustness of HDC against noise and errors is able to withstand the high error probabilities with a loss of merely 0.3% inference accuracy.

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The Nonvolatile Memory and Neuromorphic Simulation of ReS₂/h‐BN/Graphene Floating Gate Devices Under Photoelectrical Hybrid Modulations

Li,

et al. 2024

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The floating gate devices, as a kind of nonvolatile memory, obtain great application potential in logic‐in‐memory chips. The 2D materials have been greatly studied due to atomically flat surfaces, higher carrier mobility, and excellent photoelectrical response. The 2D ReS2 flake is an excellent candidate for channel materials due to thickness‐independent direct bandgap and outstanding optoelectronic response. In this paper, the floating gate devices are prepared with the ReS2/h‐BN/Gr heterojunction. It obtains superior nonvolatile electrical memory characteristics, including a higher memory window ratio (81.82%), tiny writing/erasing voltage (±8 V/2 ms), long retention (>1000 s), and stable endurance (>1000 times) as well as multiple memory states. Meanwhile, electrical writing and optical erasing are achieved by applying electrical and optical pulses, and multilevel storage can easily be achieved by regulating light pulse parameters. Finally, due to the ideal long‐time potentiation/depression synaptic weights regulated by light pulses and electrical pulses, the convolutional neural network (CNN) constructed by ReS2/h‐BN/Gr floating gate devices can achieve image recognition with an accuracy of up to 98.15% for MNIST dataset and 91.24% for Fashion‐MNIST dataset. The research work adds a powerful option for 2D materials floating gate devices to apply to logic‐in‐memory chips and neuromorphic computing.

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On the Reliability of In-Memory Computing: Impact of Temperature on Ferroelectric TCAM

Cited by 22 publications

References 13 publications

Reliable Binarized Neural Networks on Unreliable Beyond Von-Neumann Architecture

Reliable Binarized Neural Networks on Unreliable Beyond Von-Neumann Architecture

All-in-Memory Brain-Inspired Computing Using FeFET Synapses

The Nonvolatile Memory and Neuromorphic Simulation of ReS₂/h‐BN/Graphene Floating Gate Devices Under Photoelectrical Hybrid Modulations

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On the Reliability of In-Memory Computing: Impact of Temperature on Ferroelectric TCAM

Cited by 22 publications

References 13 publications

Reliable Binarized Neural Networks on Unreliable Beyond Von-Neumann Architecture

Reliable Binarized Neural Networks on Unreliable Beyond Von-Neumann Architecture

All-in-Memory Brain-Inspired Computing Using FeFET Synapses

The Nonvolatile Memory and Neuromorphic Simulation of ReS2/h‐BN/Graphene Floating Gate Devices Under Photoelectrical Hybrid Modulations

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Product

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The Nonvolatile Memory and Neuromorphic Simulation of ReS₂/h‐BN/Graphene Floating Gate Devices Under Photoelectrical Hybrid Modulations