On the Recoverable and Permanent Components of NBTI in p-Channel Power VDMOSFETs

Danković, Danijel; Manić, I.; Davidović, V.; Prijić, Aneta; Marjanovic, Milos; Ilić, Aleksandar; Prijić, Z.; Stojadinović, N.

doi:10.1109/tdmr.2016.2598557

Cited by 15 publications

(11 citation statements)

References 46 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Experiments were done at two different temperatures (150 °C and 175 °C) and values of threshold voltage shifts are obtained. Our ear-lier experiments included testing devices under many different conditions in terms of both gate voltage and temperature [9][10][11][12][13]. Experimental results are given in Figure 1.…”

Section: Methodsmentioning

confidence: 99%

“…Evolution of ∆V T through time is presented in Figure 1 Inserted graphic, and given with power law (t n ). During this evolution, distinct phases can be distinguished [4,13,30]. For every phase, the value of parameter n is different.…”

Section: Methodsmentioning

confidence: 99%

“…Taking this into consideration, our earlier papers were dealing with NBTI in p-channel power vertical double diffused MOS (VDMOS) transistors [6,[8][9][10][11][12][13]. Their reliability has been investigated under various stress conditions, such as irradiation, high electric field, NBTI, NBTI under low magnetic field, and NBTI and irradiation [13][14][15][16]. NBTI is critical for normal operation of power MOS-FETs since they are routinely operated at high current and voltage levels, which lead to both increased gate oxide fields and self-heating, thus favor NBTI.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

Mitrović¹,

Danković²,

Ranđelović³

et al. 2020

Informacije MIDEM

View full text Add to dashboard Cite

Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide semiconductor (MOS) devices simultaneously exposed to elevated temperature and negative gate voltage. This paper studies threshold voltage shift under static stress associated with the NBT stress induced buildup of both interface traps and oxide trapped charge in the commercial p-channel power VDMOSFETs IRF9520, with the goal to design an electrical model. Change of threshold voltage follow power law t n , where parameter n is different depending on the stressing phase and stressing conditions. Two modeling circuits are proposed and modeling circuit elements values are analyzed. Values of modeling circuits elements are calculated using least square method approximation conducted on obtained experimental results. Modeling results of both circuits are compared with the measured results and then further discussed.

show abstract

Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

Mitrović¹,

Danković²,

Ranđelović³

et al. 2020

Informacije MIDEM

View full text Add to dashboard Cite

show abstract

“…NBT stress-induced threshold voltage instabilities in commercial power VDMOSFETs, as well as the implications of related degradation on device lifetime have been extensively investigated in our research in the last decade [27,[42][43][44]. Although in many experiments devices have been subjected to various NBT stress (static or pulsed) and annealing conditions [9,23,25,45,46,[48][49][50][51][52], in this section a part of results obtained during static NBT stress and annealing is presented, with attention to insight into the NBTI as a result of sequential NBT stress and bias annealing steps.…”

Section: Nbt Stress Effectsmentioning

confidence: 99%

NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

et al. 2018

Self Cite

View full text Add to dashboard Cite

In this paper we provide an overview of instabilities observed in commercial power VDMOSFETs subjected to irradiation, NBT stress, and to consecutive exposure to them. The results have indicated that irradiation of previously NBT stressed devices leads to additional threshold voltage shift, while NBT stress effects in previously irradiated devices depend on the gate bias applied during irradiation and on the total dose received. This points to the importance of the order of applied stresses, indicating that for proper insight into the prediction of device behaviour not only harsh conditions, but also the order of exposure have to be considered. It has also been shown that changes in the densities of oxide trapped charge and interface traps during spontaneous recovery after each of applied stresses can be significant, thus leading to additional instability, even though the threshold voltage seems to remain stable, pointing to the need for clarifying the responsible mechanisms.

show abstract

“…Several studies in the literature [1][2][3][4][5][6][7][8] reported that p-channel power MOSFETs are subjected to degradation under High Temperature Gate Bias (HTGB) stress. Such a phenomenon, known as bias temperature instability [9], leads to the degradation of threshold voltage, which has been ascribed to both build-up of oxide charges and interface states activation [2][3][4][5][6][7]. The present work extends the previous analyses, by focusing also on the on-resistance degradation and by stressing the device at temperatures as large as 175°C (which is a relevant condition for automotive-qualified devices).…”

Section: Introductionmentioning

confidence: 99%

Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress

Magnone

Barletta

Magrì

2018

Microelectronics Reliability

View full text Add to dashboard Cite

In this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MOSFET under High Temperature Gate Bias (HTGB) stress. The impact of negative bias temperature stress is analysed by evaluating relevant figures of merit for the considered device: threshold voltage, transconductance and on-resistance. Temperatures and gate voltages as large as 175°C and-24V, respectively, are adopted to accelerate the degradation in the device. Moreover, in order to investigate the origin of degradation mechanisms we analyse the interface states generation and the charge trapping processes, the impact of a switching gate voltage during the stress phase and the recovery phase after HTGB stress.

show abstract

On the Recoverable and Permanent Components of NBTI in p-Channel Power VDMOSFETs

Cited by 15 publications

References 46 publications

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress

Contact Info

Product

Resources

About