On the possibility of sub 60 mV/decade subthreshold switching in piezoelectric gate barrier transistors

Jana, Raj K.; Snider, Gregory L.; Jena, Debdeep

doi:10.1002/pssc.201300280

Cited by 27 publications

(17 citation statements)

References 12 publications

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“…The LFN spectra measurement condition of frequency was from 10 to 1 kHz, and the drain current power spectral density (S ID ) was measured at low drain bias (V DS = 0.05 V). To locate the noise in the channel layer, the normalized current spectral density S I /I 2 at 100 Hz and gate-to-source voltage of two devices at V GS −V TH [14] from 0V to 1V was plotted (Figure 6).…”

Section: Resultsmentioning

confidence: 99%

The Characteristics of 6-Inch GaN on Si RF HEMT with High Isolation Composited Buffer Layer Design

et al. 2020

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In this study, a 50-nm Al0.05Ga0.95N back barrier (BB) layer was used in an AlGaN/GaN high-electron-mobility transistor between the two-dimensional electron gas channel and Fe-doped/C-doped buffer layers. This BB layer can reduce the channel layer. The BB layer is affected by doped carriers in the buffer layer and the conduction energy band between the channel and the buffer layers. The Ion/Ioff ratio of the BB device was 4.66 × 105, and the ratio for the device without BB was 1.91 × 103. Lower leakage currents were obtained in the BB device because of the higher conduction energy band. The 0.25-μm gate length device with the BB exhibited a high current gain cutoff frequency of 24.4 GHz, and power gain cutoff frequency of 73 GHz.

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Section: Resultsmentioning

confidence: 99%

The Characteristics of 6-Inch GaN on Si RF HEMT with High Isolation Composited Buffer Layer Design

et al. 2020

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“…As stated before, there have been numerous experimental papers on the NC-FET concept (e.g., [ 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 ]), all showing impressive results. In particular, the use of PZT in bulk MOSFETs [ 34 ] yield a record value in the

, while, in FinFETs, equally impressive results were shown with HZO [ 32 ].…”

Section: Discussionmentioning

confidence: 99%

“…Much research work followed studying the NC-effect (e.g., [ 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 ]). However, it has been debated that there is a limit to this NC-effect because of the use of multi-domain ferroelectrics [ 36 ].…”

Section: The Negative-capacitance Field-effect Transistormentioning

confidence: 99%

The Balancing Act in Ferroelectric Transistors: How Hard Can It Be?

Hueting

2018

Micromachines

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For some years now, the ever continuing dimensional scaling has no longer been considered to be sufficient for the realization of advanced CMOS devices. Alternative approaches, such as employing new materials and introducing new device architectures, appear to be the way to go forward. A currently hot approach is to employ ferroelectric materials for obtaining a positive feedback in the gate control of a switch. This work elaborates on two device architectures based on this approach: the negative-capacitance and the piezoelectric field-effect transistor, i.e., the NC-FET (negative-capacitance field-effect transistor), respectively π-FET. It briefly describes their operation principle and compares those based on earlier reports. For optimal performance, the adopted ferroelectric material in the NC-FET should have a relatively wide polarization-field loop (i.e., “hard” ferroelectric material). Its optimal remnant polarization depends on the NC-FET architecture, although there is some consensus in having a low value for that (e.g., HZO (Hafnium-Zirconate)). π-FET is the piezoelectric coefficient, hence its polarization-field loop should be as high as possible (e.g., PZT (lead-zirconate-titanate)). In summary, literature reports indicate that the NC-FET shows better performance in terms of subthreshold swing and on-current. However, since its operation principle is based on a relatively large change in polarization the maximum speed, unlike in a π-FET, forms a big issue. Therefore, for future low-power CMOS, a hybrid solution is proposed comprising both device architectures on a chip where hard ferroelectric materials with a high piezocoefficient are used.

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“…We show how this piezoelectric gate stack enables a higher on-current than in a transistor with a passive dielectric due to internal charge amplification. Finally, building upon our earlier proposals [12], [13], [14], we discuss the possibility of using the negative capacitance regime of a highly compliant piezoelectric barrier to obtain sub-60 mV/decade switching in a transistor.…”

Section: Introductionmentioning

confidence: 91%

Transistor Switches Using Active Piezoelectric Gate Barriers

Jana

Ajoy

Snider

et al. 2015

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Abstract-This work explores the consequences of introducing a piezoelectric gate barrier in a normal field-effect transistor. Because of the positive feedback of strain and piezoelectric charge, internal charge amplification occurs in such an electromechanical capacitor resulting in a negative capacitance. The first consequence of this amplification is a boost in the oncurrent of the transistor. As a second consequence, employing the Lagrangian method, we find that by using the negative capacitance of a highly compliant piezoelectric barrier, one can potentially reduce the subthreshold slope of a transistor below the room temperature Boltzmann limit of 60 mV/decade. However, this may come at the cost of hysteretic behavior in the transfer characteristics.

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On the possibility of sub 60 mV/decade subthreshold switching in piezoelectric gate barrier transistors

Cited by 27 publications

References 12 publications

The Characteristics of 6-Inch GaN on Si RF HEMT with High Isolation Composited Buffer Layer Design

The Characteristics of 6-Inch GaN on Si RF HEMT with High Isolation Composited Buffer Layer Design

The Balancing Act in Ferroelectric Transistors: How Hard Can It Be?

Transistor Switches Using Active Piezoelectric Gate Barriers

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