2018 International Conference on Electrical Sciences and Technologies in Maghreb (CISTEM) 2018
DOI: 10.1109/cistem.2018.8613430
|View full text |Cite
|
Sign up to set email alerts
|

On the Performance of FPGA Implementation of Block Matching Algorithms for Video Motion Estimation

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2022
2022
2022
2022

Publication Types

Select...
1

Relationship

0
1

Authors

Journals

citations
Cited by 1 publication
(1 citation statement)
references
References 6 publications
0
1
0
Order By: Relevance
“…Although this option offers good performance in terms of compression ratedistortion ratio, it also presents coarse drawbacks in order to be implemented on hardware, such as a complex architecture (specially the inter-prediction stage, where motion estimation is computed), preventing its implementation on hardware resources available on-board satellites [8], or an imprecise behaviour for lossless compression, among others. Different works are available in the state-of-the-art about FPGA implementations of the H.264 encoder, but focusing in particular stages whose performance is critical, such as motion estimation [9], [10], [11], [12], the intra-prediction [13], [14], quantization [15] or the encoding [16], [17]. A full hardware implementation of the H.264 encoder in baseline profile is presented in [18], consuming the 89% of slices available in a Xilinx XC6VLX240T FPGA.…”
Section: Introductionmentioning
confidence: 99%
“…Although this option offers good performance in terms of compression ratedistortion ratio, it also presents coarse drawbacks in order to be implemented on hardware, such as a complex architecture (specially the inter-prediction stage, where motion estimation is computed), preventing its implementation on hardware resources available on-board satellites [8], or an imprecise behaviour for lossless compression, among others. Different works are available in the state-of-the-art about FPGA implementations of the H.264 encoder, but focusing in particular stages whose performance is critical, such as motion estimation [9], [10], [11], [12], the intra-prediction [13], [14], quantization [15] or the encoding [16], [17]. A full hardware implementation of the H.264 encoder in baseline profile is presented in [18], consuming the 89% of slices available in a Xilinx XC6VLX240T FPGA.…”
Section: Introductionmentioning
confidence: 99%