On the Performance Improvement of Sub-sampling MPEG-2 Motion Estimation Algorithms with Vector/SIMD Architectures

Chouliaras, V.A.; Dwyer, Vincent M.; Agha, S.

doi:10.1007/11558484_75

Cited by 2 publications

(16 citation statements)

References 8 publications

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“…Fig. 11 shows an architecture of an adder tree for RB parallel PE [3,[5][6][7][8][9][10] whereas a full resolution parallel adder tree would consist of eight 8-bit adders in the first level, four 9-bit adders in the second level, two 10-bit adders in the third level, a 11-bit adder in the fourth level and a 16-bit accumulator.…”

Section: Parallel Architecture With Parallel Pe (Full Resolution and Rb)mentioning

confidence: 99%

“…All the above mentioned architectures are then connected to one at a time with the serial RISC processor (through one address and data bus, i.e., loosely coupled configurations) to investigate the reduction in the computational complexity and power consumption [3,[5][6][7][8][9][10]. The architectures with the serial RISC processor form a processor-coprocessor system.…”

Section: Pipelined Risc Processormentioning

confidence: 99%

“…The FSME is the most computational part of MPEG2 encoder, i.e., the dynamic instruction count (instruction count at run time [5][6][7][8][9][10]) of FSME is 60% -80% of the encoder's total dynamic instruction count [3,[5][6][7][8][9][10]. The real time computational complexity of the FSME algorithm on a reduced instruction set computer (RISC) processor for a common intermediate format (CIF) video sequence involves billions of 8-bit arithmetic calculations and memory accesses per second [3].…”

Section: Introductionmentioning

confidence: 99%

“…These fast subsampling algorithms have less computational complexity although their quality can deteriorate as well. When these algorithms run on the multiprocessor based system [5][6][7][8][9][10], their computational complexity reduces further. VLSI implementations of these fast ME algorithms can become complex due to irregular data flow.…”

Section: Introductionmentioning

confidence: 99%

“…In [21][22][23], we presented FSME algorithms based on low resolution pixels along with a novel correction recovery mechanism based on spatial and temporal correlations among the pixels that have the benefits of high speed, low power and low area for VLSI architectures while the quality is kept at the same level. In [7][8][9][10], we considered benefits of data level parallelism and multiprocessing in reducing the computational complexity of ME process and proposed optimized architectures with respect to area, speed and power.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Reduced bit low power VLSI architectures for motion estimation

Agha

Khan

Malik

et al. 2013

J. of Syst. Eng. Electron.

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Low power and real time very large scale integration (VLSI) architectures of motion estimation (ME) algorithms for mobile devices and applications are presented. The power reduction is achieved by devising a novel correction recovery mechanism based on algorithms which allow the use of reduced bit sum of absolute difference (RBSAD) metric for calculating matching error and conversion to full resolution sum of absolute difference (SAD) metric whenever necessary. Parallel and pipelined architectures for high throughput of full search ME corresponding to both the full resolution SAD and the generalized RBSAD algorithm are synthesized using Xilinx Synthesis Tools (XST), where the ME designs based on reduced bit (RB) algorithms demonstrate the reduction in power consumption up to 45% and/or the reduction in area up to 38%.Keywords: motion estimation (ME), very large scale integration (VLSI), reduced bit sum of absolute difference (RBSAD).

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Section: Parallel Architecture With Parallel Pe (Full Resolution and Rb)mentioning

confidence: 99%

Section: Pipelined Risc Processormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Reduced bit low power VLSI architectures for motion estimation

Agha

Khan

Malik

et al. 2013

J. of Syst. Eng. Electron.

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Use of Multiprocessing For High Throughput and Low Power Implementation of Two Dimensional Discrete Fourier Transform, Discrete Cosine Transform and MPEG Motion Estimation

Agha¹

2018

BJSTR

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In this work high throughput and low power implementations of two dimensional Discrete Fourier Transform, Discrete Cosine Transform and MPEG Motion Estimation, for battery powered real time applications, using configurable multiprocessors, are proposed and compared in terms of speed, power, area and type of application. The results show the significance of multiprocessing in reducing the computational complexity of the application depending upon the type of application and the speed, area or power constraint.

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On the Performance Improvement of Sub-sampling MPEG-2 Motion Estimation Algorithms with Vector/SIMD Architectures

Cited by 2 publications

References 8 publications

Reduced bit low power VLSI architectures for motion estimation

Reduced bit low power VLSI architectures for motion estimation

Use of Multiprocessing For High Throughput and Low Power Implementation of Two Dimensional Discrete Fourier Transform, Discrete Cosine Transform and MPEG Motion Estimation

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