On the maximum tolerable noise for reliable computation by formulas

Evans, William S.; Pippenger, Nicholas

doi:10.1109/18.669417

Cited by 59 publications

(60 citation statements)

References 5 publications

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“…A stronger result along these lines had already been proven by William Evans and Nicholas Pippenger [19], but their purely classical proof is significantly more complicated.…”

Section: Proof Of the Main Theoremmentioning

confidence: 83%

Limit on Nonlocality in Any World in Which Communication Complexity Is Not Trivial

et al. 2006

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Bell proved that quantum entanglement enables two space-like separated parties to exhibit classically impossible correlations. Even though these correlations are stronger than anything classically achievable, they cannot be harnessed to make instantaneous (faster than light) communication possible. Yet, Popescu and Rohrlich have shown that even stronger correlations can be defined, under which instantaneous communication remains impossible. This raises the question: Why are the correlations achievable by quantum mechanics not maximal among those that preserve causality? We give a partial answer to this question by showing that slightly stronger correlations would result in a world in which communication complexity becomes trivial.

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“…A stronger result along these lines had already been proven by William Evans and Nicholas Pippenger [19], but their purely classical proof is significantly more complicated.…”

Section: Proof Of the Main Theoremmentioning

confidence: 83%

Limit on Nonlocality in Any World in Which Communication Complexity Is Not Trivial

et al. 2006

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“…Evans and Pippenger [6] made some progress in this direction, showing that if a formula is constructed from independent -noisy, two-input NAND gates, then reliable computation can or cannot take place depending on whether is less than or greater than (3 0 p 7)=4 = 0:08856 . .…”

Section: Discussionmentioning

confidence: 99%

On the maximum tolerable noise of k-input gates for reliable computation by formulas

Evans

Schulman

2003

IEEE Trans. Inform. Theory

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“…The error bound for each NAND gate in c17 is ε = 0.1055, which is greater than the conventional error bound for NAND gate, which is 0.08856 [6], [7]. The error bound of the same NAND gate in voter circuit (contains 10 NAND gates, 16 NOT gates, 8 NOR gates, 15 OR gates and 10 AND gates) is ε = 0.0292, which is lesser than the conventional error bound.…”

Section: Circuit-specific Error Bounds For Fault-tolerant Computationmentioning

confidence: 94%

“…Later this work was extended for k-input gates [5] where k was chosen to be odd. For a specific even case, Evans and Pippenger [6] showed that the maximum tolerable noise level for 2-input NAND gate should be less than (3 − √ 7)/4 = 0.08856 · · ·. Later this result was reiterated by Gao et al for 2-input NAND gate, along with other results for k-input NAND gate and majority gate, using bifurcation analysis [7] that involves repeated iterations on a function relating to the specific computational component.…”

Section: A State-of-the-artmentioning

confidence: 99%

Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis

Lingasubramanian

Alam

Bhanja

2011

Microelectronics Reliability

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The application of current generation computing machines in safety-centric applications like implantable biomedical chips and automobile safety has immensely increased the need for reviewing the worst-case error behavior of computing devices for fault-tolerant computation. In this work, we propose an exact probabilistic error model that can compute the maximum error over all possible input space in a circuit-specific manner and can handle various types of structural dependencies in the circuit. We also provide the worst-case input vector, which has the highest probability to generate an erroneous output, for any given logic circuit. We also present a study of circuit-specific error bounds for fault-tolerant computation in heterogeneous circuits using the maximum error computed for each circuit. We model the error estimation problem as a maximum a posteriori (MAP) estimate, over the joint error probability function of the entire circuit, calculated efficiently through an intelligent search of the entire input space using probabilistic traversal of a binary join tree using Shenoy-Shafer algorithm. We demonstrate this model using MCNC and ISCAS benchmark circuits and validate it using an equivalent HSpice model. Both results yield the same worst-case input vectors and the highest % difference of our error model over HSpice is just 1.23%. We observe that the maximum error probabilities are significantly larger than the average error probabilities, and provides a much tighter error bounds for fault-tolerant computation. We also find that the error estimates depend on the specific circuit structure and the maximum error probabilities are sensitive to the individual gate failure probabilities.

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On the maximum tolerable noise for reliable computation by formulas

Abstract: It is shown that if a formula is constructed from noisy 2-input NAND gates, with each gate failing independently with probability ", then reliable computation can or cannot take place according as " is less than or greater than " 0 = (3? p 7)=4 = 0:08856 : : : .

Cited by 59 publications

References 5 publications

Limit on Nonlocality in Any World in Which Communication Complexity Is Not Trivial

Limit on Nonlocality in Any World in Which Communication Complexity Is Not Trivial

On the maximum tolerable noise of k-input gates for reliable computation by formulas

Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis

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