On the interface between QEMU and SystemC for hardware modeling

Yeh, Tse-Chen; Chiang, Ming-Chao

doi:10.1109/isne.2010.5669197

Cited by 7 publications

(5 citation statements)

References 3 publications

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“…There is no a native way to integrate SystemC models into QEMU, thus some co-simulation approaches have been proposed in the past [10,12,13,16]. The intent of [10] is to facilitate the development of software and device drivers for whatever operating system without spending too much effort on modifying the virtual platform itself by plugging SystemC TLM 2.0 models into the QEMUbased virtual platform.…”

Section: Qemumentioning

confidence: 99%

“…This work is further extended in [13] where the authors introduce a checkpoint-based feature to save and restore the SystemC state into the simulator. Alternatively, in [12,16], the authors propose a QEMU/SystemCbased framework for virtual platform prototyping that cannot only estimate the performance of a target system, but also co-simulate with hardware models down to the cycle accurate level.…”

Section: Qemumentioning

confidence: 99%

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On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms

Lonardi

Pravadelli

2015

VLSI-SoC: Internet of Things Foundations

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International audienceVirtual prototyping allows designers to set up an electronic system level software simulator of a full HW/SW platform to carry out SW development and HW design almost in parallel. To achieve the goal virtual prototyping tools allow the co-simulation between an efficient instruction set simulator, mainly based on dynamic binary translation of the target code, and simulation kernels for HW models, described by means of traditional hardware description languages, like, for example, SystemC. In this context, some approaches have been proposed for co-simulation between QEMU and SystemC, both from EDA companies and academic research groups. On the contrary, no paper addresses integration between Open Virtual Platform (OVP) and SystemC. Indeed, OVP models and the related simulator can be integrated into SystemC designs by using TLM 2.0 wrappers and opportune OVP APIs. However, this solution presents some disadvantages, like the incapability of supporting cycle-accurate models, and the necessity of re-design, in terms of SystemC modules, all OVP components that should be integrated in the target platform. To avoid such drawbacks, and provide an easy way to port SystemC models from a QEMU-based to an OVP-based virtual platform and vice versa, this paper presents a common co-simulation approach that works for integrating SystemC components with both QEMU and OVP. Experimental results show the effectiveness of the proposed architecture

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Section: Qemumentioning

confidence: 99%

Section: Qemumentioning

confidence: 99%

On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms

Lonardi

Pravadelli

2015

VLSI-SoC: Internet of Things Foundations

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“…There is no a native way to integrate SystemC models into QEMU, thus some co-simulation approaches have been proposed in the past [7], [9], [10], [12]. The intent of [7] is to facilitate the development of software and device drivers for whatever operating system without spending too much effort on modifying the virtual platform itself by plugging SystemC TLM 2.0 models into the QEMU-based virtual platform.…”

Section: A Qemumentioning

confidence: 99%

“…This work is further extended in [10] where the authors introduce a checkpoint-based feature to save and restore the SystemC state into the simulator. Alternatively, in [9], [12] the authors propose a QEMU/SystemC-based framework for virtual platform prototyping that cannot only estimate the performance of a target system, but also co-simulate with hardware models down to the cycle accurate level.…”

Section: A Qemumentioning

confidence: 99%

A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platforms

Cucchetto

Lonardi

Pravadelli

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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Several approaches have been proposed for cosimulation between QEMU and SystemC. On the contrary, no paper addresses integration between Open Virtual Platform (OVP) and SystemC. Indeed, OVP models and the related simulator can be integrated into SystemC designs by using TLM 2.0 wrappers and opportune OVP APIs. However, this solution presents some disadvantages, like the incapability of supporting cycle-accurate models, and the necessity of re-design, in terms of SystemC modules, all OVP components that should be integrated in the target platform. To avoid such drawbacks, and provide an easy way to port SystemC models from a QEMU-based to an OVP-based virtual platform and vice versa, this paper presents a common co-simulation approach that works for integrating SystemC components with both QEMU and OVP.

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“…Yeh and Chiang [24] used QEMU, implemented in System-C, for cycle-accurate timing of ARM processors, expanding on the interface to the QEMU code [23]. Meanwhile Chylek had been collecting program statistics through monitoring QEMU [3].…”

Section: Emulation or Simulationmentioning

confidence: 99%

Virtualized Development and Testing for Embedded Cluster Computing

McLoughlin

Bretschneider²,

Chen

2012

IJNC

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Embedded cluster processing solutions can be difficult to design if quantity and type of processors, interconnectivity technology and code partitioning are not specified in advance, and yet it may not be possible to determine these without qualitative and quantitative testing which can not be performed until hardware is available. Similar issues are faced in conventional development projects for generic embedded systems, or for generic distributed systems, but the issues are exacerbated when both attributes are combined. This paper considers issues relating to custom embedded cluster processing system development in general, before focussing on a specific example of a space-borne cluster computer using ARM processors running embedded Linux. This early example, which will be shown performing distributed synthetic aperture radar image processing, is representative of a growing number of systems in the pervasive and ambient computing fields. It illustrates many difficulties in co-developing hardware and software for specific tasks. We present one potential solution -the use of distributed virtualization to simulate the final design. An ARM cluster simulator is presented, constructed using QEMU and virtual networking, and shown used for the development and validation of distributed embedded processing tasks on a cluster-type architecture. As clusters of embedded processors, pervasive embedded networks, and the "embedded cloud" become more popular in the near future, such virtualized systems can prove useful for development and testing.

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On the interface between QEMU and SystemC for hardware modeling

Cited by 7 publications

References 3 publications

On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms

On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms

A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platforms

Virtualized Development and Testing for Embedded Cluster Computing

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