On the functional test of the cache coherency logic in multi-core systems

Acle, Julio Pérez; Cantoro, Riccardo; Sánchez, Ernesto; Reorda, M. Sonza

doi:10.1109/lascas.2015.7250453

Cited by 5 publications

(1 citation statement)

References 13 publications

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“…Another solution, FRITS (Functional Random Instruction Testing at Speed) [23], was based on test generation using random instruction sequences with pseudo-random data. Alternative cache-resident method for production testing [24,25] using random generation mechanism proves that high cost functional testers can be replaced by low-cost SBST without significant loss in fault coverage. Another approach, based on evolutionary technique was proposed in [26].…”

Section: Introductionmentioning

confidence: 99%

On Test Generation for Microprocessors for Extended Class of Functional Faults

Oyeniran¹,

Ubar²,

Jenihhin³

et al. 2020

IFIP Advances in Information and Communication Technology

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We propose a novel strategy of formalized synthesis of Software Based Self-Test (SBST) for testing microprocessors with RISC architecture to cover a large class of high-level functional faults. This is comparable to that used in memory testing which also covers a large class of structural faults such as stuck-at-faults(SAF), conditional SAF, multiple SAF and bridging faults. The approach is fully high-level, the model of the microprocessor is derived from the instruction set and architecture description, and no knowledge about gate-level implementation is needed. To keep the approach scalable, the microprocessor is partitioned into modules under test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, while for the control parts, a novel generic functional control fault model was developed. A novel method for measuring high-level fault coverage for the control parts of MUTs is proposed. The measure can be interpreted as the quality of covering the high-level functional faults, which are difficult to enumerate. We apply High-Level Decision Diagrams for formalization and optimization of high-level test generation for control parts of modules and for trading off different test characteristics, such as test length, test generation time and fault coverage. The test is well-structured and can be easily unrolled online during test execution. Experimental results demonstrate high SAF coverage, achieved for a part of a RISC processor with known implementation, whereas the test was generated without knowledge of implementation details.

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Section: Introductionmentioning

confidence: 99%

On Test Generation for Microprocessors for Extended Class of Functional Faults

Oyeniran¹,

Ubar²,

Jenihhin³

et al. 2020

IFIP Advances in Information and Communication Technology

View full text Add to dashboard Cite

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A Search Based Approach for Stress-Testing Integrated Circuits

Eljuse

Walkinshaw

2016

Search Based Software Engineering

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Abstract. In order to reduce software complexity and be power efficient, hardware platforms are increasingly incorporating functionality that was traditionally administered at a software-level (such as cache management). This functionality is often complex, incorporating multiple processors along with a multitude of design parameters. Such devices can only be reliably tested at a 'system' level, which presents various testing challenges; behaviour is often non-deterministic (from a software perspective), and finding suitable test sets to 'stress' the system adequately is often an inefficient, manual activity that yields fixed test sets that can rarely be reused. In this paper we investigate this problem with respect to ARM's Cache Coherency Interconnect (CCI) Unit. We present an automated search-based testing approach that combines a parameterised test-generation framework with the hill-climbing heuristic to find test sets that maximally 'stress' the CCI by producing much larger numbers of data stall cycles than the corresponding manual test sets.

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Comparison of Search-Based Algorithms for Stress-Testing Integrated Circuits

Eljuse

Walkinshaw

2018

Search-Based Software Engineering

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On the functional test of the cache coherency logic in multi-core systems

Cited by 5 publications

References 13 publications

On Test Generation for Microprocessors for Extended Class of Functional Faults

On Test Generation for Microprocessors for Extended Class of Functional Faults

A Search Based Approach for Stress-Testing Integrated Circuits

Comparison of Search-Based Algorithms for Stress-Testing Integrated Circuits

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