On the Determinism of Multi-core Processors

Paun, Vladimir‐Alexandru; Monsuez, Bruno; Baufreton, Philippe

doi:10.4230/oasics.fsfma.2013.32

Cited by 3 publications

(3 citation statements)

References 20 publications

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“…This section focuses upon central processing units for real-time embedded systems (RTES). Most of available processors in market are not designed specifically for the hard RTES [229]. Advanced performance improvement techniques such as pipelining, branch prediction unit (BPU), floating point unit (FPU), cache, memory management unit (MMU), frequency scaling, shared bus, etc.…”

Section: Resultsmentioning

confidence: 99%

“…Advanced performance improvement techniques such as pipelining, branch prediction unit (BPU), floating point unit (FPU), cache, memory management unit (MMU), frequency scaling, shared bus, etc. sacrifice determinism and introduce timing anomalies [229][230][231] which increases the complexity of static timing analyses [232,233].…”

Section: Resultsmentioning

confidence: 99%

“…Although achieving acceptable WCET analysis is still possible in the presence of those advanced techniques (through end-to-end testing, static analysis, and measurement-based analysis [237]), but achieving better WCET when some features (e.g., when caches are present [229]) are still an open problem. Therefore, designers tend to use simple CPUs such as RISC with less of those performance improving features for hard real-time systems.…”

Section: Resultsmentioning

confidence: 99%

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A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

Ali¹

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The reconfigurable computing (RC) aims to combine the flexibility of General-Purpose Processor (GPP) with performance of Application Specific Integrated Circuits (ASIC). There are several architectures proposed since RC’s inception in 1960s, but all have failed to become mainstream. The main factor preventing RC to become common practice is its requirement for implementers of algorithms (programmers) to be familiar with hardware design. In RC, a hardened processor cooperates with a dynamic reconfigurable Hardware Accelerator (HA) which is implemented on Field-Programmable Gate Array (FPGA). The HA implements crucial software kernel on hardware to increase performance and its design demands digital circuit expertise. In this paper a novel RC architecture is proposed that keeps the decades old programming practices intact while harnessing the power of HA. The architecture uses LLVM compiler infrastructure to receive an algorithm and then outputs the equivalent machine language, it then finds the most frequent instruction pairs and generates equivalent RC circuit called “Miniature Accelerator (MA)”. The instruction pairs are dynamically removed from pipeline and MA computed result replaces them in parallel. To demonstrate the concept the Fast Fourier Transform (FFT) algorithm which is core Digital signal processing (DSP) kernel is written in C and then executed on an ARM Cortex-M0. The execution of FFT function is improved by 14.12%. The proposed adaptive processor is fully backward compatible, compilation is automated, and no modification of exiting software or established programming paradigms is required.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

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A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

Ali¹

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Modeling Parallelization Overheads for Predicting Performance

Ranadive

Vaidya

2016

2016 International Conference on Information Systems Engineering (ICISE)

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System on Chip Based RTC in Power Electronics

Dorothy¹,

Sasilatha²

2017

Bulletin EEI

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Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.

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On the Determinism of Multi-core Processors

Cited by 3 publications

References 20 publications

A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

Modeling Parallelization Overheads for Predicting Performance

System on Chip Based RTC in Power Electronics

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