On the design of hybrid DRAM/SRAM memory schemes for fast packet buffers

García, J.; March, M.; Cerdà, Llorenç; Corbal, Jesús; Valero, Mateo

doi:10.1109/hpsr.2004.1303414

Cited by 5 publications

(5 citation statements)

References 10 publications

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“…The static variety of RAM employs only latching circuitry to manage the storage, whereas the Dynamic RAM variety uses a refreshing circuit to maintain the bit information constantly. SRAM has a faster response time and has a low packing density compared to DRAM [16]. In the comparative study, we have visualized the contribution of these data storage in a particular board.…”

Section: Memory Interfacesmentioning

confidence: 99%

Computing Boards for Internet of Things: A Comparative Survey

Dhruva¹,

Babu²,

Chakraborty³

et al. 2022

Preprint

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The performance of present-day Internet of Things (IoT) computing boards is primarily based on their architectural designs and selection of appropriate application scenarios. This paper conducts a comprehensive and comparative survey of 60 popular and commercially available IoT computing boards with respect to various performance metrics. The metrics include the capability of processor, available interfaces, available modules for communication, available memory interfaces, power system-related specifications, over-the-air programming capability, Geo-location capability, shielding capability, compatibility with other IoT computing boards, and availability of community support/integrated development environment. Further, we highlight the selected 60 IoT computing boards' architectural advancements that result in diverse real-world application capabilities. Moreover, we also discuss possible application scenarios of the IoT computing boards and their implementation details in the context of selected performance metrics. Our comparative survey on the selected 60 IoT boards can be helpful for the IoT board manufacturers and the system developers to understand the state-of-the-art designs requirements. Furthermore, the insights can be used to develop IoT computing boards for appropriate future application scenarios.<br><br>

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Section: Memory Interfacesmentioning

confidence: 99%

Computing Boards for Internet of Things: A Comparative Survey

Dhruva¹,

Babu²,

Chakraborty³

et al. 2022

Preprint

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“…Notice that an RList FIFO queue, due to its sequential data access, can be mostly kept in DRAM while supporting SDRAM like access speed (more than 100Gb/s). This is achieved by using SRAM based buffers for the head and tail parts of each list, and storing internal items in several interleaved DRAM banks [19].…”

Section: Ppq -The Power Approachmentioning

confidence: 99%

“…The merge phase starts by initialization of the BPQ with the smallest keys of the sublists (lines [17][18][19][20]. From now on until all keys have been merged, we extract the smallest key in the list (line 23), put it in the output array, deletes it from the BPQ and insert a new one, taken from the corresponding sublist which the extracted key originally came from (line 27), i.e.…”

Section: Power Sortingmentioning

confidence: 99%

Recursive design of hardware priority queues

2014

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A recursive and fast construction of an n elements priority queue from exponentially smaller hardware priority queues and size n RAM is presented. All priority queue implementations to date either require O(log n) instructions per operation or exponential (with key size) space or expensive special hardware whose cost and latency dramatically increases with the priority queue size. Hence constructing a priority queue (PQ) from considerably smaller hardware priority queues (which are also much faster) while maintaining the O(1) steps per PQ operation is critical. Here we present such an acceleration technique called the Power Priority Queue (PPQ) technique. Specifically, an n elements PPQ is constructed from 2k − 1 primitive priority queues of size k √ n (k = 2, 3, ...) and a RAM of size n, where the throughput of the construct beats that of a single, size n primitive hardware priority queue. For example an n elements PQ can be constructed from either three √ n or five 3 √ n primitive H/W priority queues. Applying our technique to a TCAM based priority queue, results in TCAM-PPQ, a scalable perfect line rate fair queuing of millions of concurrent connections at speeds of 100 Gbps. This demonstrates the benefits of our scheme when used with hardware TCAM, we expect similar results with systolic arrays, shiftregisters and similar technologies. As a by product of our technique we present an O(n) time sorting algorithm in a system equipped with a O(w √ n) entries TCAM, where here n is the number of items, and w is the maximum number of bits required to represent an item, improving on a previous result that used an Ω(n) entries TCAM. Finally, we provide a lower bound on the time complexity of sorting n elements with TCAM of size O(n) that matches our TCAM based sorting algorithm.

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“…In this section, we describe a scheme, first presented in [18], that exploits DRAM bank organization as in [17] (see Section 4). It allows a data granularity of b < B and, thus, reduces the SRAM size.…”

Section: Random Bau Scheme (Rbau)mentioning

confidence: 99%

“…SRAM only stores the tail and head of queues in order to ensure the line rate and DRAM stores the rest of them in order to ensure the large storage that is needed. To our knowledge, the hybrid design proposals made in this field are [29], [17], and [18].…”

Section: Introductionmentioning

confidence: 99%

A DRAM/SRAM memory scheme for fast packet buffers

García-Vidal

March

Cerdà

et al. 2006

IEEE Trans. Comput.

Self Cite

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Abstract-We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps.

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On the design of hybrid DRAM/SRAM memory schemes for fast packet buffers

Cited by 5 publications

References 10 publications

Computing Boards for Internet of Things: A Comparative Survey

Computing Boards for Internet of Things: A Comparative Survey

Recursive design of hardware priority queues

A DRAM/SRAM memory scheme for fast packet buffers

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