On the Design of Adaptive-Bandwidth All-Digital Phase-Locked Loops

Abstract

The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency is a fixed multiplier of the input frequency. An example is given to illustrate the design procedure and simulation results are presented to validate the adaptive characteristics with respect to the phase noise and varying bands of input frequency.

Synchronous Motor Pull-in Process Analysis

“…16,17 The recently revealed similarity between the pull in processes of SM and PLL allows extending the well-de¯ned theory of the PLL pull-in process to SM starting as well as obtaining better understanding of the underlying processes and vice-versa. 18 …”