2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2014
DOI: 10.1109/s3s.2014.7028204
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On the cryogenic performance of ultra-low-loss, wideband SPDT RF switches designed in a 180 nm SOI-CMOS technology

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“…are connected in series, which are connected in parallel between nodes L in and L out . L pkg1 and L pkg2 are the inductance of the bondwire used to package the switch integrated circuit (IC), M ij is the mutual inductance between ith and jth inductors, and R on is the resistance for the switch "on" state [18,19]. The CMOS switch is made of 12 field-effect transistors (FETs) stacked for a high-power handling capability of up to 35 dBm.…”
Section: Design Of the Tunable Bondwire Inductormentioning
confidence: 99%
“…are connected in series, which are connected in parallel between nodes L in and L out . L pkg1 and L pkg2 are the inductance of the bondwire used to package the switch integrated circuit (IC), M ij is the mutual inductance between ith and jth inductors, and R on is the resistance for the switch "on" state [18,19]. The CMOS switch is made of 12 field-effect transistors (FETs) stacked for a high-power handling capability of up to 35 dBm.…”
Section: Design Of the Tunable Bondwire Inductormentioning
confidence: 99%