On the complexity of loop fusion

Darte, Alain

doi:10.1109/pact.1999.807510

Cited by 65 publications

(78 citation statements)

References 10 publications

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“…In contrast to the idea of loop fusion from [20] and [21], we have utilized loop exchange to improve the stride access for better cache utilization, inducing better performance. In one of our approaches, we have replaced the array references with scalar variables as Callahan et al have proposed [22].…”

Section: Related Workmentioning

confidence: 99%

A Memory-Efficient Implementation of a Plasmonics Simulation Application on SX-ACE

Mathur

Matsuoka

Watanabe

et al. 2016

IJNC

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Since recent scientific and engineering simulations require heavy computations with large volumes of data, High-performance Computing (HPC) systems need a high computational capability with a large memory capacity. Most recent HPC systems adopt a parallel processing architecture, where the computational capability of the processors is increasing, however, the performance of the memory system is constrained. The bytes per flop (B/F), which is a ratio of the memory bandwidth to the flop/s, for the HPC systems have been reduced with the evolution of the HPC systems. To fully exploit the potential of the recent HPC systems, and to meet the increasing demand for large memory, it is necessary to optimize practical scientific and engineering applications, considering not only the parallelism of the applications, but also the limitations of the memory subsystems of the HPC systems. In this paper, we discuss a set of approaches to optimization of the memory access behavior of the applications, which enable their executions with improved performance on the recent HPC systems. Our approaches include memory optimizations through memory footprint controlling, restructuring of data structures for active elements, redundant data structure elimination through combined calculations and optimized re-calculation of data. To validate the effectiveness of our approaches, a plasmonics simulation application is evaluated on vector platforms NEC SX-ACE, NEC SX-9, and Intel Xeon based platform NEC LX 406-Re2. By applying our approaches to the implementation, the memory usage of the plasmonics simulation application can be reduced up to nearly 1/71 of the original, and its execution can be possible on a single node of a distributed parallel system with smaller memory capacity. The optimization results in 1.14 times faster execution on SX-ACE and 1.81 times faster execution on LX 406-Re2.

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Section: Related Workmentioning

confidence: 99%

A Memory-Efficient Implementation of a Plasmonics Simulation Application on SX-ACE

Mathur

Matsuoka

Watanabe

et al. 2016

IJNC

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“…This transformation is not only help for parallelization, but also contributes benefits to other aspects, such as reducing loop bound testing, promoting data locality etc [19]. Manjikian et al [20] presented a typical approach, which integrates both parallelism and memory locality optimization.…”

Section: Loop Transformationmentioning

confidence: 99%

A Survey of Loop Parallelization: Models, Approaches, and Recent Developments

Ye¹,

Deng²,

Zou³

2016

IJGDC

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In cloud computing era, automatic parallelization is still significant for virtualization platform. However, after several decades of development, the overall effect is still to be improved. Summary of the mainstream technology developments will be beneficial to reveal the future direction and trend. This paper reviews the technology of loop parallelization, which is the key issue in automatic parallelization. After introducing the basic models and approaches, we focus on the recent developments, on which we obtain the trend of this field and the conclusions about future.

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“…Also, because we are focusing on a limited class of applications, it is possible to develop a more accurate cost model. Darte has studied the general complexity of loop fusion [10] and has presented an approach for optimized memory allocation [11].…”

Section: Related Workmentioning

confidence: 99%

Practical Loop Transformations for Tensor Contraction Expressions on Multi-level Memory Hierarchies

Krishnamoorthy

Agrawal

2011

Lecture Notes in Computer Science

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Abstract. Modern architectures are characterized by deeper levels of memory hierarchy, often explicitly addressable. Optimizing applications for such architectures requires careful management of the data movement across all these levels. In this paper, we focus on the problem of mapping tensor contractions to memory hierarchies with more than two levels, specifically addressing placement of memory allocation and data movement statements, choice of loop fusions, and tile size selection. Existing algorithms to find an integrated solution to this problem even for two-level memory hierarchies have been shown to be expensive. We improve upon this work by focusing on the first-order cost components, simplifying the analysis required and reducing the number of candidates to be evaluated. We have evaluated our framework on a cluster of GPUs. Using five candidate tensor contraction expressions, we show that fusion at multiple levels improves performance, and our framework is effective in determining profitable transformations.

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On the complexity of loop fusion

Cited by 65 publications

References 10 publications

A Memory-Efficient Implementation of a Plasmonics Simulation Application on SX-ACE

A Memory-Efficient Implementation of a Plasmonics Simulation Application on SX-ACE

A Survey of Loop Parallelization: Models, Approaches, and Recent Developments

Practical Loop Transformations for Tensor Contraction Expressions on Multi-level Memory Hierarchies

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