On the analysis of low output impedance characteristic of flipped voltage follower (FVF) and FVF LDOs

Surkanti, Punith R.; Garimella, Annajirao; Manda, Mahender; Furth, Paul M.

doi:10.1109/mwscas.2017.8052849

Cited by 10 publications

(2 citation statements)

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“…In addition, the improvement of integration level in portable devices not only requires LDOs to provide high load current, but also requires LDOs to minimize no-load quiescent current to extend battery life [1][2]. In many existing topologies, the LDO based on the fully integrated flipped voltage follower (FVF) is an attractive choice due to its low output impedance, fast transient response, and relatively small area [3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

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A Capacitor-Free CMOS Low-Dropout Regulator with Gate-Couple Flipped Voltage Follower for SOC

Li,

Tong,

Zhang

et al. 2024

Preprint

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This paper proposes a fully integrated low dropout (LDO) regulator with gate-couple flipped voltage follower(GC-FVF). The proposed GC-FVF addresses the limited output swing issue of conventional PMOS FVF in LDOs while maintaining a low output impedance. Besides, this LDO introduces a cascode compensation loop, which, along with the low output impedance of GC-FVF, pushes the output pole far away from the unity-gain bandwidth under both light and heavy load conditions. Consequently, the LDO becomes a stable two-pole system, supporting a high loop gain of up to 100dB and significantly enhancing the load and line regulation. Key specifications include a preset output voltage of 1.8V, a minimum unregulated input voltage of 2V, a maximum output current of 100mA, a ground current of 32μA, and an active chip area of 260μm×180μm. Notably, this LDO achieves high load regulation of 4.8μV/mA and high line regulation of 13.8μV/V without the need for off-chip capacitors.

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Section: Introductionmentioning

confidence: 99%

“…Fig. 1 (b) shows the conventional PMOS FVF circuit [4]. The gate of M2 is connected to the feedback terminal V FB , forming a local feedback loop, which significantly reduces the output impedance [6].…”

Section: Introductionmentioning

confidence: 99%