On Secure Data Flow in Reconfigurable Scan Networks

Raiola, Pascal; Thiemann, Benjamin; Burchard, Jan; Atteya, Ahmed; Lylina, Natalia; Wunderlich, Hans-Joachim; Becker, Bernd; Sauer, Matthias

doi:10.23919/date.2019.8715172

Cited by 13 publications

(1 citation statement)

References 16 publications

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“…However, the key is known to the SoC integrator or the test infrastructure IP provider who inserts the HT and, thereby, these methods can only be used against external threats. Another type of prevention method is to study dependencies among cores in a RSN so as to detect possible security and trust violations and, thereafter, build a new secure network [30]. Again, this cannot prevent HT insertion given our threat model.…”

Section: Discussion On Countermeasuresmentioning

confidence: 99%

Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism

Elshamy¹,

Natale

Pavlidis³

et al. 2020

2020 IEEE European Test Symposium (ETS)

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We present a Hardware Trojan (HT) attack scenario for analog circuits. The characteristic of this HT is that it does not reside inside the victim analog circuit. Instead, it resides on an independent digital circuit on the same die where it is triggered, yet its payload is applied only to the analog circuit after being transferred via the common test infrastructure and the test interface of the analog circuit. This HT attack cannot be detected or prevented in the analog domain and it exploits the dense digital circuit to hide effectively its footprint.

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Section: Discussion On Countermeasuresmentioning

confidence: 99%

Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism

Elshamy¹,

Natale

Pavlidis³

et al. 2020

2020 IEEE European Test Symposium (ETS)

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A Complete Design-for-Test Scheme for Reconfigurable Scan Networks

2022

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Reconfigurable Scan Networks (RSNs) are widely used for accessing instruments offline during debug, test and validation, as well as for performing system-level-test and online system health monitoring. The correct operation of RSNs is essential, and RSNs have to be thoroughly tested. However, due to their inherently sequential structure and complex control dependencies, large parts of RSNs have limited observability and controllability. As a result, certain faults at the interfaces to the instruments, control primitives and scan segments remain undetected by existing test methods. In the paper at hand, Design-for-test (DfT) schemes are developed to overcome the testability problems e.g. by resynthesizing the initial design. A DfT scheme for RSNs is presented, which allows detecting all single stuck-at-faults in RSNs by using existing test generation techniques. The developed scheme analyzes and ensures the testability of all parts of RSNs, which include scan segments, control primitives, and interfaces to the instruments. Therefore, the developed scheme is referred to as a complete DfT scheme. It allows for a test integration to cover multiple fault locations can with a single efficient test sequence and to reduce overall test cost.

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