On-Probe Neural Interface ASIC for Combined Electrical Recording and Optogenetic Stimulation

Abstract

Neuromodulation technologies are progressing from pacemaking and sensory operations to full closed-loop control. In particular, optogenetics-the genetic modification of light sensitivity into neural tissue allows for simultaneous optical stimulation and electronic recording. This paper presents a neural interface application-specified integrated circuit (ASIC) for intelligent optoelectronic probes. The architecture is designed to enable simultaneous optical neural stimulation and electronic recording. It provides four low noise (2.08 μV) recording channels optimized for recording local field potentials (LFPs) (0.1-300 Hz bandwidth, 5 mV range, sampled 10-bit@4 kHz), which are more stable for chronic applications. For stimulation, it provides six independently addressable optical driver circuits, which can provide both intensity (8-bit resolution across a 1.1 mA range) and pulse-width modulation for high-radiance light emitting diodes (LEDs). The system includes a fully digital interface using a serial peripheral interface (SPI) protocol to allow for use with embedded controllers. The SPI interface is embedded within a finite state machine (FSM), which implements a command interpreter that can send out LFP data whilst receiving instructions to control LED emission. The circuit has been implemented in a commercially available 0.35 μm CMOS technology occupying a 1.95 mm 1.10 mm footprint for mounting onto the head of a silicon probe. Measured results are given for a variety of bench-top, in vitro and in vivo experiments, quantifying system performance and also demonstrating concurrent recording and stimulation within relevant experimental models.

The Neural Engine: A Reprogrammable Low Power Platform for Closed-Loop Optogenetics

“…2. This consists of two parts: one is an embedded microcontroller based neural co-processor, and the previously designed ASIC-based neural interface [12] integrated within a headstage board.…”

“…Finally, a 10pin flexible PCB cable (FPC) connector has been used to provide a connecting link between the embedded controller and the head stage. This is adaptable to commercial systems, but in this case for use with our previously described neural interface chip [12].…”

“…After that, the system is configured into sleep mode again to wait for the next interrupt. The SPI communication details are described in previous work [12]. Particularly, we designed a BMI based toolbox for three-stage processing: detection, suppression and optical simulation results are displayed in the Supplement S1conversion.…”

“…These need to take into account, light penetration [6] and Channelrhodopsin (ChR2) encoded cell performance [28]. Also, the efficiency of the LED drive circuit [12], LEDs and optrode electro-thermal-optical characteristics need to be taken into account [6].…”

“…1: It has one custom designed embedded Hardware/Software(H/W) processing system, and integrates with an ASIC based circuits for electrical recording and optical stimulations. Also, we have also incorporated communication protocols to make it compatible with both commercial data acquisition systems such as Intan as well as our previously published ASIC [12]. The remainder of this paper is structured as follows: Section II describes the hardware configuration; Section III and Section IV introduce the software architecture and BMI processing toolbox.…”