On Optimum Digital Phase-Locked Loops

Gupta, S. C.

doi:10.1109/tcom.1968.1089830

Cited by 25 publications

(6 citation statements)

References 4 publications

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“…(60) with the changes that wx = WR, cr 2 1/2F1 and Vfrs is as given in (73). The analytical results derived in A2 B{l -exp -2WRT(k + l)]}½. this section for the steady-state pdf and variance of a The first-order approximate analysis of the vector first-order DPLFC considering Rician fading can be found Markov process (x , 2) is exactly analogous to the logto agree closely with the simulation and numerical results normal case.…”

Section: ) Scrfmentioning

confidence: 99%

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Statistical Analysis of Digital Phase-Locked Loops Fading Channiels

Varanasi

Gupta

1984

IEEE Trans. Aerosp. Electron. Syst.

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Section: ) Scrfmentioning

confidence: 99%

“…A DPLFC is defined as one where the incoming signal is than analog systems [1][2][3][4][5][6][7][8][9][10][11]32]. Although most of the not only corrupted by additive Gaussian noise channel (AGN) but analyses assumed uniform sampling, a nonuniform also by a fading communication channel.…”

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confidence: 99%

Statistical Analysis of Digital Phase-Locked Loops Fading Channiels

Varanasi

Gupta

1984

IEEE Trans. Aerosp. Electron. Syst.

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“…An optimum solution for PLLs in the continuous-time domain is given by a function of the loop noise bandwidth, which can be interpreted as normal filter coefficients such as decay ratio, damping ratio, and natural frequency [1]. The same method (minimization method) can be applied in the discrete-time domain by directly employing the z-transform [3]. Finally, the filter order n, the noise bandwidth B, and the coherent integration time T (i.e., the loop update interval), which determine the number of integrators and the multiplier coefficients of the digital PLL (DPLL) and its response for different signal dynamics and noise statistics, should be chosen to achieve the design for specific user requirements [2].…”

Section: Introductionmentioning

confidence: 99%

Theoretical Upper and Lower Limits for Normalized Bandwidth of Digital Phase-Locked Loop in GNSS Receivers

Song

Pany

Won

2023

Sensors

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Determining the loop noise bandwidth and the coherent integration time is essential and important for the design of a reliable digital phase-locked loop (DPLL) in global navigation satellite system (GNSS) receivers. In general, designers set such parameters approximately by utilizing the well-known fact that the DPLL is stable if the normalized bandwidth, which is the product of the integration time and the noise bandwidth, is much less than one. However, actual limit points are not fixed at exactly one, and they vary with the loop filter order and implementation method. Furthermore, a lower limit on the normalized bandwidth may exist. This paper presents theoretical upper and lower limits for the normalized bandwidth of DPLL in GNSS receivers. The upper limit was obtained by examining the stability of DPLL with a special emphasis on the digital integration methods. The stability was investigated in terms of z-plane root loci with and without the consideration of the computational delay, which is a delay induced by the calculation of the discriminator and the loop filter. The lower limit was analyzed using the DPLL measurement error composed of the thermal noise, oscillator phase noise, and dynamic stress error. By utilizing the carrier-to-noise density ratio threshold which indicates the crossing point between the measurement error and the corresponding threshold, the lower limit of the normalized bandwidth is obtained.

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“…with unbounded derivative, the jerk, differently from the tests used in [4]. The fact that the analog loops optimized to respond to this kind of excitation loose their optimality when discretized [5] seems to be less well known.…”

Section: Introductionmentioning

confidence: 99%

GPS Digital Tracking Loops Design for High Dynamic Launching Vehicles

Roncagliolo

Blasis

Muravchik

2006

2006 IEEE Ninth International Symposium on Spread Spectrum Techniques and Applications

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Abstract-This paper describes the design of digital tracking loops for GPS receivers in a high dynamics environment, without external aiding. We adopted the loop structure of a frequencylocked loop (FLL)-assisted phase-locked loop (PLL) and design it to track accelerations steps, as those occurring in launching vehicles. We used a completely digital model of the loop where the FLL and PLL parts are jointly designed, as opposed to the classical discretized analog model with separately designed FLL and PLL. The new approach does not increase the computational burden. We performed simulations and real RF signal experiments of a fixed-point implementation of the loop, showing that reliable tracking of steps up to 40g can be achieved.

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On Optimum Digital Phase-Locked Loops

Cited by 25 publications

References 4 publications

Statistical Analysis of Digital Phase-Locked Loops Fading Channiels

Statistical Analysis of Digital Phase-Locked Loops Fading Channiels

Theoretical Upper and Lower Limits for Normalized Bandwidth of Digital Phase-Locked Loop in GNSS Receivers

GPS Digital Tracking Loops Design for High Dynamic Launching Vehicles

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