On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

Abstract

Physically Unclonable Functions (PUFs) are hardware cryptographic primitives for generating unique signatures from complex and irreproducible manufacturing variations. The uniqueness of a PUF is a fundamental performance metric that defines the extent to which a response is tied to a single device. It is often compromised if the manufacturing variations are suppressed. Though attempts have been made to improve the quality of a PUF at system level, very little work has been done at enhancing the impact of manufacturing variations on PUF circuits. In this work, we propose a novel generalized systematic framework for improving inter-die and inter-wafer manufacturing variations of a PUF circuit. The framework aligns the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. We validated the proposed technique using a large population sample of arbiter PUFs. Simulation results show that the proposed scheme has improved inter-die and inter-wafer uniqueness of arbiter PUFs by as much as 8.4% and 16% respectively. The framework can be applied to any delay-based silicon PUF structure.

Intrinsically Reliable and Lightweight Physical Obfuscated Keys

“…Using optical lithography, devices and interconnect layers are printed layer by layer in specified patterns on semiconductor wafers using a monochromatic light source focused through a lens and mask system. The entire IC fabrication process consists of hundreds of patterning, deposition, etching, doping, and polishing steps, all with inherent variabilities [14,16,23,24]. These include irregularities in etching, doping and polishing steps, light source intensity fluctuations, lens and mask defects and alignment, defocus, and interference problems [16].…”

“…The entire IC fabrication process consists of hundreds of patterning, deposition, etching, doping, and polishing steps, all with inherent variabilities [14,16,23,24]. These include irregularities in etching, doping and polishing steps, light source intensity fluctuations, lens and mask defects and alignment, defocus, and interference problems [16]. The variations in the final dimensions of a device are a combination of variations introduced by the lithographic exposure, photo-resist processing and etching steps.…”

“…Several resolution enhancement techniques, such as optical proximity correction, alternating phase shift mask, and immersion lithography, which are used to overcome sub-wavelength lithographic challenges to print ≈ 10 nm features using a much longer wavelength UV light source (193 nm) [16,24], are intentionally avoided to engineer highly sensitive lithographic variations based PUFs (litho-PUFs) [14,16]. Exploiting linewidth, length, and height variations in lithography simulation of litho-PUFs with forbidden pitch, Sreedhar et al demonstrated output voltage fluctuations as a function of focus variation in the simulated devices [14].…”

“…In PUF literature, the lithographic process has been introduced to construct PUF designs as shown in [14][15][16], see Section 2.2. However, our proposed design based on connectivity is very reliable and requires minimal randomness extraction circuitry.…”

Enhanced Arbiter PUFs using custom sized structures for reduced noise sensitivity

“…Since then, much effort has been spent on improving their statistical metrics, mainly by increasing the circuits overall delay and variance. Most prior work used additional circuitry [3], modified circuit components [4] or manipulation of the production process [5], [6]. To our best knowledge, no investigation on improving Arbiter PUFs by modifying the existing structures' sizes was done yet.…”