On embedding a hardware description language in Isabelle/HOL

Abstract

In order to define executable hardware description language while at the same time be fit for formal proofs of properties, a hardware description language VeriFormal, embedded in Isabelle/HOL, was created. VeriFormal, together with a translator and Isabelle/HOL proof facility, provides a platform for designing, simulating and reasoning about hardware designs. Building such an environment is challenging due to the fact that the designer must have expertise in programming language design, the specific domain and theorem prover. It requires selection of a language design criteria, host language, grammar, embedding approach and techniques and mechanisms to address determinism and termination issues. When the language in question is a hardware description language, it requires specialized treatment of events, their scheduling, data types and assignments. In this paper, we report on our experience of embedding hardware description language VeriFormal in theorem prover Isabelle/HOL. In particular, the structure and execution of programs in the context of theorem provers and their impact on the overall language design are discussed. Among the main features of VeriFormal include formal semantics of the language, support for mechanical reasoning about designs and compiler and type checking of modules using Isabelle/HOL as well as VeriFormal type checkers.

Formal Verification of Hardware Components in Critical Systems

“…As a future work, we plan to build a translator to automatically translate circuit designs as Boolean functions in a natural style to the formalized (in Coq) Boolean algebra. Furthermore, to complete a formal electronic design flow, we intend to build a logic synthesis tool for translation from formal register-transfer level representation of the circuit (e.g., in VeriFormal, [49,69]) to gate-level representation as Boolean functions.…”

“…Meredith et al [67] defined executable semantics for Verilog by embedding it in the tool Maude [68] with rewriting logic as the underlying logic. Inspired from [67], Wilayat et al [49,69] introduced a formal language, VeriFormal: a hardware description language with mathematical foundation. VeriFormal is a formal replica of description language Verilog deeply embedded in Isabelle/HOL theorem prover.…”

Proving Reliability of Image Processing Techniques in Digital Forensics Applications

“…Meredith et al [18] defined an executable semantics by embedding hardware description language (HDL) Verilog in the theorem prover [19]. Inspired from [18], Khan et al [20,21] defined an HDL, dubbed as VeriFormal, in the more powerful and expressive higher-order logic of proof assistant Isabelle/HOL. VeriFormal is available with an executable simulator and a prototype translator to translate existing design descriptions in Verilog to VeriFormal.…”

An Executable Formal Model of the VHDL in Isabelle/HOL

“…Their simplified version of Bluespec, called Fe-Si, is deeply embedded language. In a recent effort, we defined a domain-specific language dubbed as VeriFormal [16]. The language VeriFormal is a formal version of Verilog which is deeply embedded in Isabelle/HOL.…”

“…The project adopts a multi-layer verification approach where we formalise each layer separately and use a refinement-based approach to show that properties proved at the top level are preserved at the lower levels. This work closely connects with the other components of the project such as the formal modelling and verification of verilog [8] and the SPARCv8 instruction set architecture for the LEON3 processor [9], [10], a verification framework for concurrent C-like programs [11], and automated reasoning techniques for separation logic [12]- [14]. For easy integration, these related sub-projects partly determine our software choices such as Isabelle/HOL and hardware choices such as LEON3 and VHDL.…”