On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication

Sravani, M. M.; Sundararajan, Ananiah Durai

doi:10.1109/tvlsi.2022.3148275

Cited by 11 publications

(7 citation statements)

References 41 publications

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“…Reduced Area at this stage compensates for the additional data path and Area rendered by the subsequent Bio-Hash skimmer and Fusion logic. Earlier reported architecture in [21], has been designed such that the padder and permutation modules operate in 'split-transfer' mode through handshake protocol. First, the message input converted to a sequence of 32/64 bits by padding, is processed to yield 'r' bits through a high throughput load-shift-store (LSS) scheme.…”

Section: B Sha-3 Architecture Reviewmentioning

confidence: 99%

“…1. The lead-lag counter logic initiates the first stage to perform the round operation for rounds (0-11) followed by the remaining round (12)(13)(14)(15)(16)(17)(18)(19)(20)(21)(22)(23) by the second stage. For the subsequent rounds 'counter 1' leads and the 'counter 2' lags.…”

Section: B Sha-3 Architecture Reviewmentioning

confidence: 99%

“…The existing Cascade-P SHA-3 architecture is mostly suitable for multi-block message, as the cascaded structure runs on reduced clock count for streaming the input messages. However, for a single-block biometric data, no significant improvement in clock count is noted, further the architecture fails to provide better Area performances [21] that is essential for a compact application such as the e-Health Record System. The proposed pseudo cascaded architecture that includes a standalone 'round 0' operation provides better Area performance.…”

Section: ) Pre-processing Of the Biometric Traitsmentioning

confidence: 99%

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Bio-Hash Secured Hardware e-Health Record System

Sravani

Sundararajan

2023

IEEE Trans. Biomed. Circuits Syst.

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Dual securing strategy for all-hardware e-Health Record System is designed and developed for improved security and reduced Hardware Execution Time (HET). A compact novel Hashed Minutiae Random Fusion (HMRF) logic enables to achieve high irreversibility and increased non-reconstruction capability of the bio-template based Bio-Hash key. AES encryption of the patient's health data during Write mode and decryption during View mode are seamlessly performed through the lively generated key, yielding low HET through optimized slack. On the other hand, biometric controlled key retrieval during Read only mode for a single user access is performed on the prescrambled Bio-Hash key, to enable bypassed decryption (direct) of the Patient's health data for self-review. The proposed pseudo cascaded SHA-3 (Secured Hash Algorithm) architecture being the first stage in HMRF, hashes the biometric minutiae of both Patient (P) and Medical Practitioner (MP) with low Latency. Thus, facilitating in further lowering of the HET by reducing the clock count by one. The subsequent Random Compression Logic (RCL) skims the hashed value from 512 to 128 bits along with the help of priority compression logic (PCL) to achieve reduced bits handling thereby lowering the Power budget. Four fusion modes are leveraged to achieve better randomization and non-recoverability. Implementation of this HMRF logic on Virtex-7 (V7) FPGA device has yielded low Area of 4191 slices. Lesser Area of 11.6 % is observed for this HMRF module compared to the reported design, excluding level shifter and PCL. Further, low HETs of 8.2/8.3/8.0 ns during Write/View/Read only modes respectively are being noticed. The dynamic Power dissipated for the three modes of operations are found to be 1.418/1.420/0.676 watts respectively.

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Section: B Sha-3 Architecture Reviewmentioning

confidence: 99%

Section: B Sha-3 Architecture Reviewmentioning

confidence: 99%

Section: ) Pre-processing Of the Biometric Traitsmentioning

confidence: 99%

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Bio-Hash Secured Hardware e-Health Record System

Sravani

Sundararajan

2023

IEEE Trans. Biomed. Circuits Syst.

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“…The introduction of SHA-3, with its unique SPONGE construction, aims to enhance cryptographic security and address potential vulnerabilities identified in SHA-1. A hardware implementation of SHA-3 has been explored in various studies [11,12,13,14,15,16,17,18,19,20]. Some studies [11,12] emphasize resource savings by employing the folding mechanism, which allows for the reuse of resources multiple times.…”

Section: Introductionmentioning

confidence: 99%

A multimode SHA-3 accelerator based on RISC-V system

Huynh,

Dang,

Tran

et al. 2024

IEICE Electron. Express

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Nowadays, almost all fields cannot lack security, from the essential encryption/decryption to hash function algorithms. The Secure Hash Algorithm 3 (SHA-3) with four modes, SHA3-224/256/384/512, is a known new hash function due to being more secure than its predecessors, SHA-1 and SHA-2. While hardware implementations of SHA-3 have been extensively studied, the primary focus has often been on optimizing the KECCAK algorithm. This paper introduces an efficient multimode SHA-3 architecture (MS3) featuring configurable buffers and a sub-pipeline KECCAK design. These innovations aim to save resources and boost throughput, respectively. Furthermore, MS3 is integrated with the reduced instruction set computer five (RISC-V) system as a hardware accelerator via the TileLink bus. This integration enables MS3 to communicate with RISC-V for configuration purposes and utilize direct memory access (DMA) for efficient data transfer with memory. Experimental results on the Cyclone IV E platform demonstrate MS3 achieving approximately 500 Mbps throughput across all modes, with DMA achieving a throughput of 540.21 Mbps. Additionally, our design exhibits superior efficiency compared to existing works on Virtex 5, 6, and 7 FPGA platforms.

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“…Enhancing the performance of a KECCAK circuit implemented in embedded circuits is a significant challenge. Currently, the KECCAK algorithm is used in a wide range of applications requiring high security, such as smart cards and mobile communication [ 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 ]. Consequently, there is a need to enhance the KECCAK algorithm’s resilience against multiple physical attacks, such as fault attacks.…”

Section: Introductionmentioning

confidence: 99%

High-Speed Hardware Architecture Based on Error Detection for KECCAK

Mestiri

Barraj

2023

Micromachines

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The hash function KECCAK integrity algorithm is implemented in cryptographic systems to provide high security for any circuit requiring integrity and protect the transmitted data. Fault attacks, which can extricate confidential data, are one of the most effective physical attacks against KECCAK hardware. Several KECCAK fault detection systems have been proposed to counteract fault attacks. The present research proposes a modified KECCAK architecture and scrambling algorithm to protect against fault injection attacks. Thus, the KECCAK round is modified so that it consists of two parts with input and pipeline registers. The scheme is independent of the KECCAK design. Iterative and pipeline designs are both protected by it. To test the resilience of the suggested detection system approach fault attacks, we conduct permanent as well as transient fault attacks, and we evaluate the fault detection capabilities (99.9999% for transient faults and 99.999905% for permanent faults). The KECCAK fault detection scheme is modeled using VHDL language and implemented on an FPGA hardware board. The experimental results show that our technique effectively secures the KECCAK design. It can be carried out with little difficulty. In addition, the experimental FPGA results demonstrate the proposed KECCAK detection scheme’s low area burden, high efficiency and working frequency.

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On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication

Cited by 11 publications

References 41 publications

Bio-Hash Secured Hardware e-Health Record System

Bio-Hash Secured Hardware e-Health Record System

A multimode SHA-3 accelerator based on RISC-V system

High-Speed Hardware Architecture Based on Error Detection for KECCAK

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