On core and more: a design perspective for systems-on-a-chip

Pees, Stefan; Vaupel, M.; Zivojnovic, V.; Meyr, H.

doi:10.1109/asap.1997.606850

Cited by 5 publications

(2 citation statements)

References 22 publications

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“…Reusing IP-cores is becoming more and more popular, especially for large Systems on a Chip [3,4]. Famous commercial examples (e.g., [5,6]) have fixed I/O interfaces, no configurable instruction set and register data size.…”

Section: Introductionmentioning

confidence: 99%

Soft-cores generation by instruction set analysis

Fin

Fummi

Perbellini

2001

Proceedings of the 14th International Symposium on Systems Synthesis - ISSS '01

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The popularity of Soft Cores is rapidly increasing. Their integration in a design requires their synthesis and optimization, thus their application is more complex than the use of Hard Cores. However, Soft Cores can be customized to the design constraints, thus promising to lead to more efficient designs. The decision of using Soft or Hard Cores is difficult since it is a trade-off between performance, cost and design time. The parametrization methodology presented in this paper gives to the Soft Core providers the possibility of putting on the market easily customizable versions of their Cores. Moreover, the proposed Soft-Cores generator helps the designer to select between the Soft and the Hard-Core version of a processor.

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Section: Introductionmentioning

confidence: 99%

Soft-cores generation by instruction set analysis

Fin

Fummi

Perbellini

2001

Proceedings of the 14th International Symposium on Systems Synthesis - ISSS '01

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“…Since time to market and product lifetime are shrinking while, at the same time, circuit complexity is growing, the traditional way of designing integrated circuits has to be altered to achieve higher efficiency than before. As the complexity of circuits increases, there is urgent need for new design methodologies, that allow fast development of demanding applications up to complete system-on-a-chip integrations [1] [2].…”

Section: Introductionmentioning

confidence: 99%

A parametrizable hybrid stack-register processor as soft intellectual property module

Luthi¹,

Röwer²,

Stadler³

et al.

Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)

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Hardware/Software Co-Design usually encounters serious problems to guarantee strong real-time constraints while serving many interrupt routines. We present an enhanced register-based RISC processor, which is capable of launching every interrupt routine within two clock cycles. This processor is implemented as soft IP-Module and features a customizable instruction set, extensive parameterization, and a synthesis model with separate core and interfaces. An automatic derivation of adequate test vectors from the current parameter setting verifies the correct functionality. The authors want to thank KTI (Swiss Commission for Technology and Innovations) for funding this project.

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