Abstract:We presents an on-chip tunable wide ranged multiple output CMOS voltage reference based on non-volatile highly precise field programmable floating gate transistors. The reference is outfit for both sub 1V and above 1V applications. The circuit design consists of basic beta multiplier configuration and offers a strategy of making the current sourcing circuit and reference generating circuit as independent units. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. Simulation results show… Show more
“…In contrast that in the proposed DVMC with M delay elements is 26M + 54K + 78 which includes 26 transistors for bias voltage generators; we used the voltage generator shown in Ref. [18]. So, it is conclude that the proposed DVMC requires 114 more transistors than the traditional DVMC.…”
Section: Area Overheadmentioning
confidence: 98%
“…[17] was used; the clock period can be set every 5.2 ps from 500 ps to 1,000 ps. We used an on-chip tunable wide ranged multiple output voltage reference circuit [18] to generate the bias voltage of V biasp and V biasn for the DTC inverter; the generator of Ref. [18] can generate bias voltages with 13-bit resolution [19].…”
Section: Resolutionmentioning
confidence: 99%
“…We used an on-chip tunable wide ranged multiple output voltage reference circuit [18] to generate the bias voltage of V biasp and V biasn for the DTC inverter; the generator of Ref. [18] can generate bias voltages with 13-bit resolution [19]. In the calibration of the DTC inverter, the maximal value N is 16.…”
Section: Resolutionmentioning
confidence: 99%
“…The voltages shown in the Tables can be generated by using a voltage generator with 6-bit resolution or higher, which the voltage generator of Ref. [18] meets with a large margin. In summary, the comparison shown in Table 1 is valid even when considering practical voltage generator.…”
This paper presents a novel calibration method for Delay Value Measurement Circuit (DVMC), a class of embedded time to digital converter (TDC), using a variable clock generator for accurate delay measurement. The proposed method uses a design for calibration as well as a variable clock generator. The design utilizes a delay time controllable (DTC) inverter. It also uses two OR-NAND gates which work as selectors; we reconfigure the construction of the ring oscillator (RO) in DVMC when calibrating the DTC inverter. The proposed scheme accomplishes more accurate calibration compared to the traditional calibration which only uses the variable clock generator. For example, when using a variable clock generator with the resolution of 5.2 ps, the resolution of the proposed method is 0.58 ps while the traditional method is 5.2 ps.
“…In contrast that in the proposed DVMC with M delay elements is 26M + 54K + 78 which includes 26 transistors for bias voltage generators; we used the voltage generator shown in Ref. [18]. So, it is conclude that the proposed DVMC requires 114 more transistors than the traditional DVMC.…”
Section: Area Overheadmentioning
confidence: 98%
“…[17] was used; the clock period can be set every 5.2 ps from 500 ps to 1,000 ps. We used an on-chip tunable wide ranged multiple output voltage reference circuit [18] to generate the bias voltage of V biasp and V biasn for the DTC inverter; the generator of Ref. [18] can generate bias voltages with 13-bit resolution [19].…”
Section: Resolutionmentioning
confidence: 99%
“…We used an on-chip tunable wide ranged multiple output voltage reference circuit [18] to generate the bias voltage of V biasp and V biasn for the DTC inverter; the generator of Ref. [18] can generate bias voltages with 13-bit resolution [19]. In the calibration of the DTC inverter, the maximal value N is 16.…”
Section: Resolutionmentioning
confidence: 99%
“…The voltages shown in the Tables can be generated by using a voltage generator with 6-bit resolution or higher, which the voltage generator of Ref. [18] meets with a large margin. In summary, the comparison shown in Table 1 is valid even when considering practical voltage generator.…”
This paper presents a novel calibration method for Delay Value Measurement Circuit (DVMC), a class of embedded time to digital converter (TDC), using a variable clock generator for accurate delay measurement. The proposed method uses a design for calibration as well as a variable clock generator. The design utilizes a delay time controllable (DTC) inverter. It also uses two OR-NAND gates which work as selectors; we reconfigure the construction of the ring oscillator (RO) in DVMC when calibrating the DTC inverter. The proposed scheme accomplishes more accurate calibration compared to the traditional calibration which only uses the variable clock generator. For example, when using a variable clock generator with the resolution of 5.2 ps, the resolution of the proposed method is 0.58 ps while the traditional method is 5.2 ps.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.