On-chip power-on reset strategy and I/O power supply detection for VLSI circuits

Burdia, Danut; Lazar, G. A.; Lazăr, Luminiţa-Camelia; Buzatu, N. R.

doi:10.1109/isscs.2009.5206160

Cited by 4 publications

(1 citation statement)

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“…10 It is expected that POR-PG circuit works reliably at various supply voltage levels utilizing proper power-up sequence of multi supply IC cores. 4 They should operate at low supply voltages designed and integrated in purely digital fabrication processes and ICs. 2,5 Operating supply voltage of POR-PG circuit has to be lower than that of the IC in which it is being integrated.…”

Section: Design Considerationsmentioning

confidence: 99%

A Compact Cmos Power-on-Reset Pulse Generator Design With Low-Power and Wide Operation Range

2010

J CIRCUIT SYST COMP

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A compact power-on-reset pulse generator (POR-PG) circuit with a low-power and low-voltage operation capability is presented. Proposed POR-PG was fabricated in 0:5 m 2P3M CMOS process. It was determined from simulations and measurements that proposed POR-PG works supply voltage levels between 1.8 V and 3.3 V and supply voltage rise times between 100 ns and 1 ms. POR-PG has very small silicon footprint. Layout size of proposed POR-PG circuit was 120 m Â 55 m in 0:5 m CMOS process. Comparing with other POR-PG circuits in the literature, proposed design enjoys lowest power consumption (< 6 W), smallest silicon footprint, widest supply voltage range, and additional features such as brown-out detection capability. These achieved by using a unique cascadable POR delay element that consumes very low-power.

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Section: Design Considerationsmentioning

confidence: 99%