On-chip networks for mixed-criticality systems

Petrakis, Polydoros; Abuteir, Mohammed; Grammatikakis, Miltos D.; Papadimitriou, Kyprianos; Obermaisser, Roman; Owda, Zaher; Papagrigoriou, Antonis; Soulie, Michael; Coppola, Marcello

doi:10.1109/asap.2016.7760787

Cited by 4 publications

(3 citation statements)

References 14 publications

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“…A brief comparison of approaches to multiprocessor scheduling of MCS is provided by Osmolovskiy et al [2016]. The evaluation of communications within MCS is considered by the work of Napier et al [2016] and Petrakis et al [2016].…”

Section: Systems Issuesmentioning

confidence: 99%

A Survey of Research into Mixed Criticality Systems

2017

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This survey covers research into mixed criticality systems that has been published since Vestal's seminal paper in 2007, up until the end of 2016. The survey is organised along the lines of the major research areas within this topic. These include single processor analysis (including fixed priority and EDF scheduling, shared resources and static and synchronous scheduling), multiprocessor analysis, realistic models, and systems issues. The survey also explores the relationship between research into mixed criticality systems and other topics such as hard and soft time constraints, fault tolerant scheduling, hierarchical scheduling, cyber physical systems, probabilistic real-time systems, and industrial safety standards. CCS Concepts: •Computer systems organization → Real-time system specification; •Software and its engineering → Real-time schedulability; Real-time systems software;

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Section: Systems Issuesmentioning

confidence: 99%

A Survey of Research into Mixed Criticality Systems

2017

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“…Petrakis et al 52 introduced the integration of MPSoC with NoC in MC systems. They examined whether the NoC capacity is su±cient to meet deadlines for external HC workloads while also serving the lower internal critical workloads.…”

Section: Speci¯c Applications In MC Systemsmentioning

confidence: 99%

A Review of Recent Techniques in Mixed-Criticality Systems

Chai

Zhang

Sun

et al. 2019

J CIRCUIT SYST COMP

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Unlike traditional embedded systems that almost have only one criticality level, many complex embedded systems nowadays are mixed-critical and are more and more widely used. There has been a lot of research on mixed-criticality (MC) systems. In this paper, we present a survey on the MC systems on these research. First, we discuss the exaltation of the schedulability of MC systems. As improving schedulability may lead to quality-of-service (QoS) reduction of MS systems. Therefore, we investigate the approaches to solve this problem. Improving QoS of MS systems may inevitably increase the energy consumption. Then, we introduce the researches that take the energy efficiency as a design requirement of MC systems. Few MC systems regard fault-tolerance as the design requirement, thus, we extensively investigate fault-tolerance of MC systems. In addition, we introduce some of the main applications for MC systems.

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“…Multiple cores residing in a single chip (MPSoC) exist towards mixed-criticality system includes dependability, security, and different block access with shared resources. The outside network real-time messages are communicating to MPSoC using a gateway [2]. In general, the network gateway is a node which connects two different networks with different transmission protocols and simplifies the internet connectivity into one electronic device.…”

Section: Introductionmentioning

confidence: 99%

Performance Evaluation of Network Gateway Design for NoC based System on FPGA Platform

Guruprasad¹,

B.S²

2019

IJACSA

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Network on Chip (NoC) is an emerging interconnect solution with reliable and scalable features over the System on Chip (SoC) and helps to overcome the drawbacks of bus-based interconnection in SoC. The multiple cores or other networks have a boundary which is limited to communicate with devices, which are directly connected to it. To communicate with these multiple cores outside the boundary, the NOC requires the gateway functionality. In this manuscript, a cost-effective Network Gateway (NG) model is designed, and also the interconnection of a network gateway with multiple cores are connected to the NoC based system is prototyped on Artix-7 FPGA. The NG mainly consists of Serializer and deserializer for transmitting and receiving the data packets with proper synchronization, temporary register to hold the network data, electronic crossbar switch is connected with multiple cores which are controlled by switch controller. The NG with the Router and different sizes of NoC based system is designed using congestionfree adaptive-XY routing. The implementation results and performance evaluation are analyzed for NG based NoC in terms of average Latency and maximum Throughput for different Packet Injection Ratio (PIR). The proposed Network gateway achieves low latency and high throughput in NoC based systems for different PIR.

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On-chip networks for mixed-criticality systems

Cited by 4 publications

References 14 publications

A Survey of Research into Mixed Criticality Systems

A Survey of Research into Mixed Criticality Systems

A Review of Recent Techniques in Mixed-Criticality Systems

Performance Evaluation of Network Gateway Design for NoC based System on FPGA Platform

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