2012
DOI: 10.1109/tns.2012.2218257
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On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

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Cited by 46 publications
(9 citation statements)
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“…† Similar parallelization for SET pulse-width measurement is reported in[5], but a preliminary work of this paper[6] was published before[5].…”
mentioning
confidence: 80%
“…† Similar parallelization for SET pulse-width measurement is reported in[5], but a preliminary work of this paper[6] was published before[5].…”
mentioning
confidence: 80%
“…The SET is a momentary voltage spike at a node of an integrated circuit generated by a single energetic particle passing through or near the junctions creating an ionization track. As illustrated in Figure 2.9, the peak voltage affects non-latched elements such as combinational logic (LOVELESS et al, 2012). The resulting effect may propagate any significant distance through the combinational logic and, if it is not masked, can reach a memory element where can be sampled causing a fault (WIRTH;…”
Section: Soft Errorsmentioning
confidence: 99%
“…Although experimental measurement of SETs has been accomplished with a variety of techniques [13,14,15,16], few works could distinguish SETs originating from PMOS transistors (P-hit) and NMOS transistors (N-hit) directly. For instance, a circuit design for separating SET is described in [17].…”
Section: Introductionmentioning
confidence: 99%