On-Chip Interconnection Architecture of the Tile Processor

Wentzlaff,; Griffin,; Hoffmann, A.; Бао,; Edwards,; Ramey,; Mattina,; Miao,; Brown,; Agarwal,

doi:10.1109/mm.2007.4378780

Cited by 628 publications

(392 citation statements)

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“…But for the purpose of implementation and experimentation alone, the job allocator has been optimized for a 2D-mesh architecture, such as the Tilera TilePro64 [4,30]. The Tilera TilePro64 processor has 64 tiles interconnected with a 2D-Mesh Network-On-Chip (NoC) interconnect.…”

Section: Methodsmentioning

confidence: 99%

“…Hence, many chip vendors have abandoned uniprocessor scaling and have instead resorted to doubling the number of cores per chip. With current single microprocessor chips of up to 100's of cores on a die [1][2][3][4] available, a 1000 core chip might soon be reality [8,30], and specialized computing devices, e.g., graphic processing units (GPUs), already support such scales today.…”

Section: An Era Of Large-scale Manycoresmentioning

confidence: 99%

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Distributed Job Allocation for Large-Scale Manycores

Ramachandran

Mueller

2016

Lecture Notes in Computer Science

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As today's manycore processors already feature over 64 cores and as tomorrow's are slated to contain 1000s, it is important to design operating system techniques that can efficiently cope with this scale of resource coordination. The current state-of-the-art in manycore processor architectures has evolved from traditional bus-based architectures over rings to mesh-based Network-on-Chip (NoC) interconnects. This implies an increasing potential for scalable message passing. However, contemporary operating systems heavily rely on single system images with shared memory constructs that may not scale well to large core counts. To address these challenges, we devise a distributed message passing only system comprised of so-called "pico-kernels" per core. They are controlled by dedicated "micro-kernels" topologically centered within a set of cores that cooperatively comprise the overall operating system in a peer-to-peer fashion.Such a system promotes rethinking and redesigning of various operating system services focusing on scalability as the primary design constraint. We consider the challenges of distributed allocation of jobs, each comprised of a set of tasks to be mapped to disjoint cores. A naive solution performing fragmented allocations may quickly escalate to deadlocks, where jobs hold and wait for cores in circular dependencies. To tackle these challenges, we propose a deadlock free distributed job allocation protocol. We have devised two policies for avoiding deadlocks, namely active cancellation and sequencer-based atomic broadcast. The protocol and the two policies have been implemented and evaluated on a Tilera TilePro64 processor with 64 cores on a single socket. Results show that for sparse job allocations active cancellation provides less job allocation overhead while for denser job allocations the sequencer-based atomic broadcast provides less overhead.

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Section: Methodsmentioning

confidence: 99%

Section: An Era Of Large-scale Manycoresmentioning

confidence: 99%

Distributed Job Allocation for Large-Scale Manycores

Ramachandran

Mueller

2016

Lecture Notes in Computer Science

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“…Moreover, and without any loss of generality, we bound the upper and lower PLL frequencies between 1 GHz and 100 MHz, providing a realistic and reasonably flexible environment. The Tilera iMesh NoC is similarly clocked up to 1 GHz [36].…”

Section: Methodsmentioning

confidence: 99%

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Zoni

Terraneo

Fornaciari

2015

Journal of Systems Architecture

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a b s t r a c tNetworks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of multi-and many-cores, but their non negligible power consumption requires ad hoc power-performance design methodologies. In this perspective, several proposals exploited the possibility to dynamically tune voltage and frequency for the interconnect, taking steps from traditional CPU-based power management solutions. However, the impact of the actuators, i.e. the limited range of frequencies for a PLL (Phase Locked Loop) or the time to increase voltage and frequency for a Dynamic Voltage and Frequency Scaling (DVFS) modules, are often not carefully accounted for, thus overestimating the benefits. This paper presents a control-based methodology for the NoC power-performance optimization exploiting the Dynamic Frequency Scaling (DFS). Both timing and power overheads of the actuators are considered, thanks to an ad hoc simulation framework. Moreover the proposed methodology eventually allows for user and/or OS interactions to change between different high level power-performance modes, i.e. to trigger performance oriented or power saving system behaviors. Experimental validation considered a 16-core architecture comparing our proposal with different settings of threshold-based policies. We achieved a speedup up to 3 for the timing and a reduction up to 33.17% of the power ⁄ time product against the best threshold-based policy. Moreover, our best control-based scheme provides an averaged power-performance product improvement of 16.50% and 34.79% against the best and the second considered threshold-based policy setting.

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“…SSI was a good match for bus-based multiprocessors in the past. However, bus-based designs do not scale well (even beyond four processors) and have been replaced by mesh interconnects (e.g., Hypertransport, Quick Path Interconnect) with currently up to 16 cores per socket and, for high core counts, tile-based architectures with 2D meshed network-onchip (NoC) interconnects [4], [5], [23], [18], [3].…”

Section: Introductionmentioning

confidence: 99%

NoCMsg: Scalable NoC-Based Message Passing

Zimmer

Mueller

2014

2014 14th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing

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Abstract-Current processor design with ever more cores may ensure that theoretical compute performance still follows past increases (resting from Moore's law), but they also increasingly present a challenge to hardware and software alike. As the core count increases, the network-on-chip (NoC) topology has changed from buses over rings and fully connected meshes to 2D meshes. The question is which programming paradigm provides the scalability needed to ensure performance is close to theoretical peak, where 2D meshes provide the most scalable design to date.This work contributes NoCMsg, a low-level message passing abstraction over NoCs. NoCMsg is specifically designed for large core counts in 2D meshes. Its design ensures deadlock free messaging for wormhole Manhattan-path routing over the NoC. Experimental results on the TilePro hardware platform show that NoCMsg can significantly reduce communication times by up to 86% for single packet messages and up to 40% for larger messages compared to other NoC-based message approaches. Results further demonstrate the potential of NoC messaging to outperform shared memory abstractions by up to 93% as core counts and inter-process communication increase, i.e., we observe that shared memory scales up to about 16 cores while message passing performs well beyond that threshold on this platform. To the best of our knowledge, this is the first head-on comparison of shared memory and advanced message passing specifically designed for NoCs on an actual hardware platform with larger core counts on a single socket.

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On-Chip Interconnection Architecture of the Tile Processor

Cited by 628 publications

References 3 publications

Distributed Job Allocation for Large-Scale Manycores

Distributed Job Allocation for Large-Scale Manycores

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

NoCMsg: Scalable NoC-Based Message Passing

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