On-Chip Fuzzy Logic Synthesis of a New Ischemic and Non-Ischemic Heartbeat Classifier

Fuente-Cortes, Gisela De La; Díaz-Méndez, Alejandro; Flores‐Verdad, Guillermo Espinosa; González-Díaz, Víctor R.

doi:10.1109/tcsii.2020.3007464

Cited by 4 publications

(3 citation statements)

References 12 publications

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“…However, experimental demonstrations of neuro-symbolic computing using memristors are yet to be achieved. In conventional CMOS-based hardware, the implementation of neuro-sybolic system is limited by the complexity in representing knowledge in symbolic form, which imposes a notable increase in storage, computing time and power consumption ( 27 ). Moreover, the intrinsic variability of memristors usually leads to performance degradation, especially in large arrays.…”

Section: Introductionmentioning

confidence: 99%

Stochastic neuro-fuzzy system implemented in memristor crossbar arrays

Shi,

Zhang,

Cui

et al. 2024

Sci. Adv.

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Neuro-symbolic artificial intelligence has garnered considerable attention amid increasing industry demands for high-performance neural networks that are interpretable and adaptable to previously unknown problem domains with minimal reconfiguration. However, implementing neuro-symbolic hardware is challenging due to the complexity in symbolic knowledge representation and calculation. We experimentally demonstrated a memristor-based neuro-fuzzy hardware based on TiN/TaO x /HfO x /TiN chips that is superior to its silicon-based counterpart in terms of throughput and energy efficiency by using array topological structure for knowledge representation and physical laws for computing. Intrinsic memristor variability is fully exploited to increase robustness in knowledge representation. A hybrid in situ training strategy is proposed for error minimizing in training. The hardware adapts easier to a previously unknown environment, achieving ~6.6 times faster convergence and ~6 times lower error than deep learning. The hardware energy efficiency is over two orders of magnitude greater than field-programmable gate arrays. This research greatly extends the capability of memristor-based neuromorphic computing systems in artificial intelligence.

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Section: Introductionmentioning

confidence: 99%

Stochastic neuro-fuzzy system implemented in memristor crossbar arrays

Shi,

Zhang,

Cui

et al. 2024

Sci. Adv.

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“…8 However, they have limited speed, higher power consumption, more design complexity, and a considerable chip area due to the need for large data converters. 9,10 On the other hand, analog fuzzifiers with better power savings, fewer transistor counts, smaller chip area, and reasonable speed are more interesting than the other design methods. 11,12 Various MFGs have been proposed in the literature based on the conventional complementary metal-oxide-semiconductor (CMOS) technology.…”

Section: Introductionmentioning

confidence: 99%

“…Digital fuzzifiers present suitable noise immunity and resolution for general‐purpose applications 8 . However, they have limited speed, higher power consumption, more design complexity, and a considerable chip area due to the need for large data converters 9,10 . On the other hand, analog fuzzifiers with better power savings, fewer transistor counts, smaller chip area, and reasonable speed are more interesting than the other design methods 11,12 .…”

Section: Introductionmentioning

confidence: 99%

Ultra‐efficient fully programmable membership function generator based on independent double‐gate FinFET technology

Jooq

Behbahani

Moaiyeri

2023

Circuit Theory & Apps

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SummaryThis paper demonstrates an ultra‐efficient, fully programmable membership function generator (MFG) utilizing independent double‐gate (IDG) FinFET technology. The proposed MFG can produce s‐shaped, z‐shaped, triangular, and trapezoidal membership functions. By employing only six transistors, the designed MFG provides full controllability over the height, position, width, and slope of the generated waveforms. Without using any additional transistor and changing the dimensions, the proposed MFG can calibrate the slope of the output based on the back‐gate bias voltage of the IDG‐FinFETs. According to our extensive simulations, the proposed MFG shows promising improvements in transistor count (70%), power‐delay‐product (PDP) (80%), and maximum absolute error (61%) as compared with its state‐of‐the‐art counterparts. To benchmark the functionality of the proposed MFG in practical applications, our generated membership function is exploited as the neuron's activation function in a multilayer perceptron (MLP) neural network. The simulation results indicate that the training process of the simulated MLP with the proposed MFG closely tracks the results obtained from the ideal MLP with the sigmoid activation function. A figure of merit (FoM) is defined considering the hardware efficiency and accuracy of the neural networks to evaluate the entire performance of the proposed MFG. The FoM simulations demonstrate that the proposed MFG presents an excellent trade‐off between hardware performance and accuracy in neural network applications. Our results emphasize that the proposed MFG is a potential candidate for designing high‐performance on‐chip neural networks.

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